Q2VLSI Design

A CMOS 2-input NAND gate consists of two PMOS transistors connected in parallel between VDD and the output node (forming the pull-up network), and two NMOS transistors connected in series between the output node and ground (forming the pull-down network), with both PMOS gates and both NMOS gates driven by the same two inputs A and B respectively. The output is pulled low only when both NMOS transistors conduct (both A and B high, providing a complete series path to ground), and is pulled high whenever at least one PMOS conducts (at least one of A, B low), directly implementing the NAND (NOT-AND) function Y=(A.B)'.