Q8VHDL

(a) Serial Adder

library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

entity serial_adder is
    port (
        clk, reset : in  STD_LOGIC;
        A, B       : in  STD_LOGIC;   -- one bit of each operand per clock
        Sum        : out STD_LOGIC
    );
end serial_adder;

architecture behavioral of serial_adder is
    signal carry : STD_LOGIC := '0';
begin
    process(clk, reset)
    begin
        if reset = '1' then
            carry <= '0';
        elsif rising_edge(clk) then
            carry <= (A and B) or (B and carry) or (A and carry);
        end if;
    end process;
    Sum <= A xor B xor carry;
end behavioral;

A serial adder adds two multi-bit binary numbers one bit-pair at a time (least-significant bit first), across successive clock cycles, rather than adding all bit positions simultaneously as a parallel (combinational) adder does - it uses a single full-adder logic block (implementing the standard Sum and Cout equations, as examined in detail elsewhere in this examination) combined with a single D flip-flop that stores the carry-out from one clock cycle and feeds it back as the carry-in for the next clock cycle's bit-pair addition. This design trades speed (requiring N clock cycles to add two N-bit numbers, compared to a single clock cycle for a parallel adder) for a dramatic reduction in hardware resource usage (needing only one full adder and one flip-flop regardless of the operand bit-width, compared to N full adders needed for an N-bit parallel adder), making serial addition an attractive choice in extremely area/resource-constrained applications where processing speed is a secondary concern compared to minimizing gate count.

(b) Mealy vs Moore FSM

As discussed in detail in relation to the alternate 2021 paper's Unit IV question, a Moore machine's output depends only on the current state, changing only synchronously with state transitions (typically on a clock edge), giving it a clean, glitch-free output timing but generally requiring more states than an equivalent Mealy machine for the same overall function, since a Moore machine sometimes needs a separate state purely to represent a distinct output condition that a Mealy machine could instead associate directly with a state transition (edge) rather than needing its own dedicated state. A Mealy machine's output instead depends on both the current state AND the current input values simultaneously, allowing the output to change immediately in response to an input change (potentially even within the same clock cycle, asynchronously with respect to the clock, since the output is a direct combinational function of state and input) rather than only at the next clock edge - this generally allows a Mealy machine to be implemented with fewer states than an equivalent Moore machine, and to respond one clock cycle 'faster' to input changes in specific circumstances, but at the cost of potential output glitches (since a combinational output can briefly and momentarily reflect any transient glitch on its input signals, unlike a Moore machine's output which is always a stable, registered value). The choice between Moore and Mealy style for a given design is generally driven by whether glitch-free, purely clock-synchronous output timing (favoring Moore) or minimum state count and fastest possible input-to-output response (favoring Mealy) is the more important design priority for that specific application.

The serial adder and the Moore/Mealy comparison in this question connect naturally, since a serial adder's control could itself be described as a small Mealy or Moore machine layered on top of the datapath shown, coordinating how many bit-serial cycles to run and when to signal completion for a fixed operand width, exactly the same control-unit-plus-datapath separation discussed in relation to the shift-and-add multiplier data path examined elsewhere in this examination. Viewed this way, the serial adder's single carry flip-flop functions simultaneously as both a datapath storage element (holding the arithmetic carry value) and, in a loose sense, as the 'state' of a trivial one-bit Mealy machine whose output (Sum) is a combinational function of both this stored carry state and the current A, B inputs each cycle - reinforcing that the Moore/Mealy classification framework applies not only to abstract control state machines but to arithmetic circuits with feedback as well.

In choosing between a bit-serial adder and a fully parallel adder for a given application, the Mealy-versus-Moore timing trade-off discussed above has a loose practical analogy: just as a Mealy machine trades additional combinational output-glitch risk for a faster, more immediate response and fewer states, a serial adder trades a slower, multi-cycle latency (needing N clock cycles for an N-bit sum) for a dramatically smaller, cheaper combinational and sequential hardware footprint (a single full adder and flip-flop) compared to a parallel adder's N full adders operating simultaneously - in both cases the underlying engineering decision is a speed-versus-resource trade-off, and recognizing this shared pattern across seemingly different topics (FSM output style, and arithmetic circuit architecture) is a useful way to organize and remember the many distinct design trade-offs that appear throughout digital design coursework.

The serial adder examined here also provides a useful concrete setting to revisit the general Mealy-versus-Moore output-timing distinction discussed in part (b): the serial adder's Sum output ('Sum <= A xor B xor carry;') is a purely combinational expression depending simultaneously on both the current A, B inputs and the currently-held carry state, meaning Sum can, in principle, glitch momentarily if A or B change asynchronously mid-cycle before the next active clock edge - exactly the kind of combinational-output glitch risk associated with Mealy-style outputs discussed generally in part (b) - whereas if the design instead registered Sum through an additional output flip-flop before presenting it externally, it would gain the glitch-free, purely-state-dependent output timing characteristic of a Moore-style design, at the cost of one additional clock cycle of output latency, concretely illustrating the same general speed-versus-glitch-immunity trade-off described abstractly in the Moore/Mealy comparison.

It is also worth noting that the serial adder as coded computes only the running Sum bit each cycle and does not itself accumulate or shift the individual sum bits into a complete multi-bit result register, meaning a complete practical serial-adder application would need an additional shift register (clocked by the same clk signal) to capture each cycle's Sum bit into successive bit positions, exactly analogous in structure to the shift registers examined elsewhere in this examination, reinforcing that the shift-register building block appears repeatedly across many different sequential-circuit applications throughout this question paper, from simple serial-to-parallel conversion, to the multiplier and divider datapaths, to this serial-adder's implicit need for an output-collecting shift register in any complete real implementation.

Finally, it is worth noting that a complete practical implementation combining these two sub-topics might use a Moore or Mealy finite state machine (of the kind discussed generally in part (b)) specifically to sequence and control a serial adder's operation across the correct number of clock cycles for a given operand width, asserting a completion signal once all bits have been processed - directly connecting the abstract FSM classification discussed here to the concrete multi-cycle arithmetic circuit examined alongside it, and reinforcing that most non-trivial sequential digital systems are naturally described as some combination of a datapath (the serial adder's full-adder-plus-carry-flip-flop hardware) and a controlling FSM (sequencing the datapath's operation), exactly the same datapath/control-unit split emphasized throughout the Unit V arithmetic-circuit questions in this examination.