Q1VHDL

(a) CPLD vs FPGA

A CPLD (Complex Programmable Logic Device) is built from a comparatively small number of large, macrocell-based logic blocks (each macrocell typically containing a sum-of-products combinational logic array plus an optional flip-flop), interconnected through a centralized, fully-connected (or near-fully-connected) programmable interconnect matrix - this architecture gives CPLDs highly predictable, fixed propagation delays (since signal routing paths are simple and direct through the centralized interconnect), non-volatile configuration storage (typically Flash or EEPROM-based, so the device retains its programming when power is removed and is immediately functional at power-up without needing external reconfiguration), and comparatively modest logic capacity (typically a few hundred to a few thousand equivalent logic gates) - CPLDs are therefore well suited to smaller glue-logic applications, simple state machines, address decoding, and applications requiring instant-on operation and predictable timing (such as basic system control logic and power management sequencing) at low cost.

An FPGA (Field Programmable Gate Array) is instead built from a very large number of small, fine-grained logic blocks (each typically containing one or a few lookup tables, LUTs, plus flip-flops), interconnected through a distributed, segmented routing fabric rather than a single centralized matrix, along with dedicated hard blocks for common functions (block RAM, DSP multiply-accumulate units, and in modern FPGAs, embedded processor cores and high-speed transceivers) - this architecture gives FPGAs vastly greater logic capacity (from tens of thousands to millions of equivalent logic gates), making them suitable for large, complex digital designs (complete processor cores, complex signal processing pipelines, entire communication protocol stacks). However, most FPGAs use volatile (SRAM-based) configuration memory, meaning they must be reconfigured from an external configuration memory (Flash, or loaded by a host processor) every time power is applied, unlike a CPLD's instant-on non-volatile operation - FPGAs are therefore preferred for large, high-performance, or reconfigurable applications (video/image processing, high-speed networking, prototyping of custom processor architectures), while CPLDs remain preferred for smaller, simpler, instant-on control-logic applications where their non-volatile configuration and predictable timing are more valuable than raw logic capacity.

(b) Routing

Routing is the physical-design stage (following placement) in which the design-automation tool determines the actual metal interconnect wiring paths needed to electrically connect the outputs and inputs of all the placed logic gates/blocks according to the netlist produced by synthesis, using the specific programmable interconnect resources available on the target FPGA/CPLD (or, for an ASIC, using available metal routing layers) - for FPGAs specifically, routing must select a path through the device's segmented, distributed routing fabric (a network of programmable interconnect switches and wire segments of various lengths) connecting each logic block's output to every input it needs to drive, subject to the constraint that each individual wire segment and switch can only be used by one signal at a time (avoiding routing conflicts), and the routing tool aims to find a valid, congestion-free routing solution that also meets the design's timing requirements (minimizing the propagation delay of critical signal paths) - routing quality (how directly and with how little congestion signals can be routed) directly affects both the achievable maximum clock frequency and, in FPGAs specifically, whether a given design can be successfully fit and routed onto a specific device at all, since severe routing congestion can sometimes make an otherwise logically-fitting design unroutable on a particular device without design or constraint changes.

Beyond the architectural differences already described, CPLDs and FPGAs also differ in how their programmable interconnect affects timing predictability, which is often the deciding practical factor for choosing between them. A CPLD's centralized interconnect matrix means that essentially any macrocell can reach any other macrocell through a comparably short, fixed number of switch stages, so propagation delay for a given design is largely independent of exactly which macrocells are used and how the logic happens to be placed - this predictability is precisely why CPLDs are favored for simple control logic where guaranteed, easily-calculated worst-case timing matters more than raw density. An FPGA's distributed, segmented routing fabric, by contrast, means that the delay between two logic blocks depends heavily on their physical distance and on how congested the routing is in that region of the chip, so timing in an FPGA design is far more placement-and-routing-dependent and generally requires the place-and-route tool's timing-driven optimization (and post-route static timing analysis) to confirm the design actually meets its target frequency, rather than being predictable purely from the source code alone.

This distinction also carries through to how designs migrate between the two device families. Because CPLD macrocells implement sum-of-products logic directly, VHDL code relying heavily on wide, complex Boolean equations (as opposed to LUT-friendly small-fan-in logic) tends to map efficiently onto a CPLD but can consume a disproportionate number of an FPGA's small LUTs if the same equation does not decompose well into few-input lookup tables; conversely, FPGA-oriented designs that rely on dedicated hard blocks (block RAM, multiplier/DSP slices) have no direct CPLD equivalent and must be reimplemented behaviorally in ordinary logic if ported to a CPLD, at a significant cost in macrocell usage. This is one of the practical reasons that CPLD and FPGA target devices are usually decided early in a project, since a design's VHDL coding style is often implicitly shaped around the resource structure of its intended target device family.

It is also worth relating the CPLD/FPGA distinction to the ASIC design flow discussed in the alternate version of this question: an FPGA or CPLD implementation can be seen as a pre-fabricated, generic array of logic and interconnect resources that is merely configured (rather than physically manufactured) to realize a specific design, which is precisely why FPGA/CPLD designs skip the floorplanning, physical placement-and-routing-to-silicon, and fabrication/tape-out steps of the full custom ASIC flow, instead going directly from synthesis to a much faster and cheaper device-specific place-and-route and bitstream-generation step - this fundamental difference (configuring a pre-built generic chip versus fabricating a new custom chip from scratch) is the underlying reason FPGA and CPLD designs can be verified in real hardware within hours of completing the RTL, whereas an ASIC design commits to months of fabrication turnaround time and cannot be corrected once tape-out has occurred.