Q5Computer Architecture

(i) Parallel Processing

Parallel processing refers to the simultaneous execution of multiple computational tasks or instructions using multiple processing elements, aiming to increase computational speed and throughput beyond what a single sequential processor could achieve. It is realized at multiple levels — instruction-level (pipelining, superscalar execution), data-level (SIMD/vector processing), and task/process-level (multiple cores or processors executing independent programs) — and is essential for high-performance computing applications such as scientific simulation, image processing, and large-scale data analytics, where problems can be decomposed into independent or loosely-coupled sub-computations executed concurrently.

(ii) Microprogrammed computers

A microprogrammed computer implements its control unit using a microprogram — a sequence of microinstructions stored in a special control memory (control store) — rather than using fixed, hardwired logic circuits to generate control signals. Each machine-level instruction is decoded to select a corresponding sequence of microinstructions, and each microinstruction directly specifies the micro-operations (register transfers, ALU operations, control signal activations) needed for one step of instruction execution. This approach (introduced by Maurice Wilkes) makes the control unit design more systematic, flexible, and easier to modify or extend (simply by rewriting microcode) compared to hardwired control, at some cost in execution speed due to the extra level of indirection through the control memory.

(iii) Associative Memory

Associative memory, also called Content-Addressable Memory (CAM), is a type of memory that is accessed by its content rather than by a specific address. Given a search argument (or a portion of it via a mask register), the memory hardware simultaneously (in parallel) compares the argument against all stored words and returns the address(es)/data of any matching entries, making search operations extremely fast (effectively O(1) regardless of memory size) compared to conventional memory requiring sequential search. It is used in applications requiring very fast lookup, such as cache memory tag comparison, database search acceleration, and network routing tables, though its parallel comparison hardware makes it considerably more expensive per bit than conventional RAM.

(iv) Stacks and Queues

A stack is a linear data structure that follows the Last-In-First-Out (LIFO) principle, where elements are inserted (pushed) and removed (popped) only from one end, called the top. Stacks are fundamental to subroutine call/return mechanisms (storing return addresses and local variables in the 'call stack'), expression evaluation (e.g., postfix expression computation), and recursive algorithm implementation. A queue is a linear data structure that follows the First-In-First-Out (FIFO) principle, where elements are inserted (enqueued) at one end (the rear) and removed (dequeued) from the other end (the front), and is commonly used for buffering tasks such as I/O device request handling, process scheduling, and any scenario requiring elements to be processed strictly in the order they arrived.

(v) Subroutines

A subroutine (or procedure/function) is a self-contained, reusable block of instructions designed to perform a specific, well-defined task, which can be invoked (called) from multiple points within a program without duplicating its code. When a CALL instruction is executed, the return address (the address of the instruction following the call) is saved, typically by pushing it onto the stack, and control transfers to the subroutine's starting address; upon completion, a RETURN instruction pops the saved return address from the stack and transfers control back to the calling program, resuming execution exactly where it left off. This mechanism supports modular program design, code reuse, and (via the stack-based storage of return addresses and parameters) enables recursive subroutine calls.