Q3Computer Architecture

An instruction format specifies the layout of an instruction in terms of its constituent fields — typically an opcode field and one or more address fields — and different formats represent different trade-offs between instruction length/complexity and the number of memory/register references required to complete an operation.

Three-address instruction format: the instruction specifies three operand addresses — two source operands and one destination — e.g., ADD R1, R2, R3 computes R1 = R2 + R3. This format produces compact, efficient programs (fewer total instructions) since a single instruction fully specifies a complete operation, but each instruction itself is longer since it must encode three addresses, increasing instruction word size and hence memory bandwidth requirements for instruction fetch.

Two-address instruction format: the instruction specifies two addresses, where one address serves as both a source operand and the destination (overwriting it), e.g., ADD R1, R2 computes R1 = R1 + R2. This reduces instruction length compared to three-address format at the cost of destroying one of the original operand values, requiring extra MOV instructions if the original value needs to be preserved.

One-address (accumulator-based) instruction format: the instruction specifies only one explicit address, with the second operand and the destination implicitly being a special CPU register called the accumulator, e.g., ADD M computes AC = AC + M[address]. This yields very short instructions but requires the accumulator to be explicitly loaded and stored around each operation via separate LOAD/STORE instructions, increasing the total instruction count for complex expressions.

Zero-address (stack-based) instruction format: the instruction specifies no explicit operand addresses at all; instead, operands are implicitly taken from the top of a push-down stack, and results are pushed back onto the stack, e.g., an ADD instruction pops the top two stack values, adds them, and pushes the result. This requires the operands to be already loaded onto the stack via separate PUSH instructions (converting the expression to postfix/Reverse Polish Notation), producing very compact instructions but a longer overall instruction sequence, and is well suited to expression evaluation and simple compiler code generation.

Illustrative example: evaluating the expression X = (A + B) × (C − D) in each format demonstrates the trade-off: in three-address form, it takes two instructions — ADD T1, A, B and SUB T2, C, D and MUL X, T1, T2 (three instructions, each fully specifying its operands); in accumulator (one-address) form, it requires a longer sequence of LOAD/ADD/STORE/LOAD/SUB/STORE/LOAD/MUL/STORE instructions cycling data through the accumulator; and in zero-address (stack) form, the postfix expression A B + C D − × is evaluated using a sequence of PUSH and implicit-operand ADD/SUB/MUL instructions that operate purely on the stack top, illustrating how the same computation requires very different instruction counts and formats depending on the chosen architecture.

Design trade-off summary: the choice of instruction format has direct implications for CPU hardware design and compiler complexity. Formats with more address fields (three-address) require wider instruction words and more complex instruction decoding hardware but minimize total program length and the number of memory/register accesses, generally favored in RISC-style register-rich architectures where instruction fetch bandwidth is cheap relative to register-file access. Formats with fewer address fields (one-address, zero-address) simplify the instruction decoder and reduce instruction word size, historically valuable when memory was expensive and slow, but shift more of the workload onto explicit data-movement instructions, increasing the dynamic instruction count executed per computation. Most modern general-purpose processors adopt a two- or three-address, register-based format as the best practical balance, reserving zero-address (stack) and pure one-address (accumulator) styles for specialized contexts such as expression evaluation in virtual machines (e.g., the Java Virtual Machine uses a stack-based instruction format) or historically simple early computer designs.