Q6Computer Architecture

Pipelining is a technique for implementing instruction-level parallelism within a single processor by overlapping the execution of multiple instructions. The instruction execution process is divided into a sequence of independent stages — commonly Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write-Back (WB) — each handled by dedicated hardware. While one instruction is in its Execute stage, the next instruction can simultaneously be in its Decode stage, and the one after that in its Fetch stage, much like an assembly line where multiple products are at different stages of completion simultaneously.

In an ideal k-stage pipeline processing n instructions, once the pipeline is full, one instruction completes every clock cycle rather than every k cycles (as in non-pipelined sequential execution), giving an ideal speedup approaching a factor of k. However, real pipelines suffer from hazards that can stall this ideal throughput: structural hazards (resource conflicts, e.g., two stages needing the same hardware unit simultaneously), data hazards (an instruction depends on the result of a preceding instruction not yet completed, requiring stalls or forwarding/bypassing), and control hazards (branch instructions whose target is not known until later stages, potentially requiring the pipeline to be flushed of incorrectly fetched instructions). Techniques like forwarding, branch prediction, and out-of-order execution are used in modern processors to mitigate these hazards and keep the pipeline as full as possible, maximizing the practical throughput gain from pipelining.

Speedup analysis: for a k-stage pipeline processing n instructions, the total execution time is approximately (k + n − 1) clock cycles, compared to k·n cycles for fully sequential (non-pipelined) execution of the same n instructions. As n grows large, the speedup factor approaches k (the number of pipeline stages), since the fixed pipeline-fill overhead of (k−1) cycles becomes negligible relative to the n cycles of steady-state, one-instruction-per-cycle throughput. This is why modern processors use deep pipelines (often 10-20+ stages) to maximize theoretical throughput, though in practice the achievable speedup is reduced below this ideal by the hazards discussed above, motivating the extensive branch-prediction and hazard-mitigation hardware found in contemporary CPU designs.