Q2Computer Architecture

Computer memory technologies span a hierarchy characterized by trade-offs between speed, cost per bit, storage capacity, and volatility (whether contents are retained without power).

Registers: the fastest memory technology, implemented directly within the CPU using flip-flops, offering access times comparable to the processor's clock cycle, but extremely limited in number/capacity (a few dozen to a few hundred registers) and the most expensive per bit.

SRAM (Static RAM): used for cache memory, SRAM stores each bit using a bistable flip-flop circuit (typically six transistors), requiring no periodic refresh and offering very fast access times (a few nanoseconds), but consuming more chip area and power per bit than DRAM, making it costlier and used only where speed is paramount (L1/L2/L3 caches).

DRAM (Dynamic RAM): used for main memory, DRAM stores each bit as a charge on a tiny capacitor (using a single transistor per cell), making it much denser and cheaper per bit than SRAM, but the capacitor charge leaks over time, requiring periodic refresh circuitry to rewrite the data, and access is somewhat slower than SRAM. Variants like SDRAM, DDR, DDR2/3/4/5 SDRAM are synchronized with the system clock and pipeline multiple accesses to increase effective bandwidth for main memory use.

ROM (Read-Only Memory) and its variants: ROM is a non-volatile memory technology (retains data without power) whose contents are typically fixed at manufacture (mask ROM) or, in more flexible variants, can be programmed and in some cases reprogrammed: PROM can be electrically programmed once by the user; EPROM can be erased using ultraviolet light and reprogrammed; and EEPROM (and its descendant, flash memory) can be electrically erased and reprogrammed in-circuit, without special equipment, making it the basis of modern firmware storage, USB drives, and SSD storage cells.

Secondary/auxiliary storage: magnetic disk (hard disk drives) and solid-state drives (SSDs, built from flash memory/EEPROM technology) provide much larger capacity at much lower cost per bit than main memory, but with significantly higher (though for SSDs, much improved over HDDs) access latency, and are non-volatile, used for long-term storage of programs and data, and as the backing store for virtual memory paging/swapping.

Memory hierarchy principle: these technologies are organized into a hierarchy — registers, then cache (SRAM), then main memory (DRAM), then secondary storage (SSD/disk) — with speed and cost per bit decreasing, and capacity increasing, as one moves down the hierarchy, exploiting the principle of locality of reference so that the small amount of fast, expensive memory near the top effectively services the vast majority of memory accesses, while the much larger, cheaper, slower memory near the bottom provides the necessary total capacity, achieving a system that approaches the speed of the fastest technology at close to the cost per bit of the slowest.

Quantitative comparison of access times and costs: to make this hierarchy concrete, typical relative access latencies (illustrative, not exact for any specific chip) might be: CPU registers, under 1 nanosecond; SRAM cache (L1), roughly 1-4 nanoseconds; SRAM cache (L2/L3), roughly 10-40 nanoseconds; DRAM main memory, roughly 50-100 nanoseconds; SSD (flash-based) secondary storage, roughly 20,000-100,000 nanoseconds (tens of microseconds); and magnetic hard disk, roughly 5,000,000-10,000,000 nanoseconds (several milliseconds) due to mechanical seek and rotational delay. This roughly 5-6 order-of-magnitude spread in latency across the hierarchy is precisely why the memory hierarchy design — keeping the small working set of currently relevant data in the fastest levels — has such a dramatic impact on overall system performance; a program whose memory accesses are poorly localized (causing frequent cache misses and page faults down to disk) can run orders of magnitude slower than one with good locality, even on identical hardware.

Emerging and specialized memory technologies: beyond the conventional hierarchy, several specialized technologies address particular needs — NVRAM (Non-Volatile RAM) and newer technologies like MRAM (Magnetoresistive RAM) and phase-change memory aim to combine DRAM-like speed with the non-volatility of flash, potentially reshaping future memory hierarchies by blurring the traditional volatile/non-volatile boundary; and video/graphics memory (VRAM, GDDR variants) is specifically optimized for the high-bandwidth, highly parallel access patterns required by graphics processing, often using wider data buses and different latency-versus-bandwidth trade-offs than conventional system DRAM. Understanding the full spectrum of memory technologies — from the fastest, most expensive registers down through the largest, cheapest secondary storage — is essential for computer architects to make informed trade-offs when designing systems for specific performance, cost, and power budgets.

Volatility and power implications: the volatile technologies (registers, SRAM, DRAM) all lose their stored contents the instant power is removed, meaning any system relying solely on these technologies must have some non-volatile backing store to preserve data across power cycles — this is precisely the role played by ROM/flash-based firmware (which must survive power-off to allow the system to boot) and by secondary storage (which must retain user data and installed programs indefinitely without continuous power). Non-volatile technologies, while essential for persistence, generally exhibit slower write speeds and, in the case of flash memory, a limited number of write/erase cycles before cells begin to wear out, which is why memory-hierarchy and file-system designers must additionally account for write-endurance and wear-leveling considerations specifically when using flash-based (SSD/EEPROM) storage, a concern that does not arise for the purely volatile technologies higher in the hierarchy.

Summary table of trade-offs: ranking the technologies from fastest/most-expensive/smallest-capacity to slowest/cheapest/largest-capacity gives the ordering: registers, SRAM cache, DRAM main memory, flash/SSD, magnetic disk — with volatility present only in the first three and non-volatility characterizing the latter two, illustrating that the memory-technology landscape is fundamentally organized around this single unifying speed-cost-capacity-volatility trade-off curve that every computer architecture course and system design decision must ultimately navigate.

Conclusion: no single memory technology can simultaneously deliver the speed of registers, the capacity of magnetic disk, and the cost-effectiveness of both at once, which is why practical computer systems are always built as a coordinated hierarchy combining several of these technologies rather than relying on any one in isolation — an architectural principle that has remained fundamentally stable even as the specific technologies at each level (SRAM, DRAM, flash) have continued to advance in density and speed over successive hardware generations.