{"pinia":{"ui":{"prefs":{"theme":"system","textScale":"md","fontFamily":"sans","reducedMotion":false,"highContrast":false}},"academy":{"universities":[],"universitySummaries":[{"slug":"rtu","name":"RTU","fullName":"Rajasthan Technical University","branches":[{"slug":"first-year-common","name":"First Year (Common)"},{"slug":"computer-science","name":"Computer Science"},{"slug":"mechanical","name":"Mechanical"},{"slug":"civil","name":"Civil"},{"slug":"ai-data-science","name":"AI & Data Science"},{"slug":"ee-ec-eee","name":"EE / EC / EEE"}]},{"slug":"aktu","name":"AKTU","fullName":"Dr. A. P. J. Abdul Kalam Technical University","branches":[{"slug":"first-year-common","name":"First Year (Common)"},{"slug":"computer-science","name":"Computer Science"}]}],"activePapers":[{"id":"computer-architecture-2024-5E1780","title":"Computer Architecture (2024)","subjectSlug":"computer-architecture","subjectName":"Computer Architecture","universitySlug":"rtu","branchSlug":"ee-ec-eee","year":3,"semester":5,"paperCode":"5E1780","questions":[{"id":"computer-architecture-2024-5E1780-pA-q1","number":1,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.1. What is Cache Memory?"}],"answer":{"summary":"Cache memory is a small, high-speed memory placed between the CPU and main memory that stores frequently accessed data/instructions to reduce average memory access time.","explanation":[{"type":"paragraph","content":"Cache memory is a small-capacity, very fast semiconductor memory (typically SRAM) positioned between the CPU and main (DRAM) memory. It exploits the principle of locality of reference (temporal and spatial) by holding copies of recently and frequently accessed instructions/data, so the CPU can retrieve them at near-processor speed instead of waiting for the much slower main memory, thereby significantly reducing the average memory access time and improving overall system performance."}]}},{"id":"computer-architecture-2024-5E1780-pA-q2","number":2,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.2. Explain the input out-put processor."}],"answer":{"summary":"An I/O processor (IOP) is a specialized processor that manages input/output operations independently of the CPU, handling data transfer between peripherals and memory to free the CPU for computation.","explanation":[{"type":"paragraph","content":"An Input-Output Processor (IOP) is a dedicated processing unit that takes over the responsibility of managing data transfers between peripheral devices and main memory, executing its own I/O programs (channel programs) independently of the main CPU. Once the CPU issues a start-I/O command specifying the task, the IOP autonomously handles device control, data movement, and error checking, interrupting the CPU only upon completion — this offloading allows the CPU to continue executing other instructions concurrently, greatly improving system throughput in high-I/O-volume environments like mainframes."}]}},{"id":"computer-architecture-2024-5E1780-pA-q3","number":3,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.3. Define Computer Architecture."}],"answer":{"summary":"Computer Architecture refers to the conceptual design and functional structure of a computer system, defining its instruction set, data formats, addressing modes, and the interface between hardware and software.","explanation":[{"type":"paragraph","content":"Computer Architecture is the study and specification of a computer system's functional behavior as seen by a programmer — encompassing the instruction set architecture (ISA), data types and formats, addressing modes, register organization, and I/O mechanisms. It defines the attributes visible to a systems programmer, distinct from computer organization (which deals with the operational, hardware-level implementation details like control signals and circuit design), and serves as the blueprint that both hardware designers and compiler/software developers use to ensure programs execute correctly on the machine."}]}},{"id":"computer-architecture-2024-5E1780-pA-q4","number":4,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.4. What is Von-Neuman Architecture? Define."}],"answer":{"summary":"Von-Neumann Architecture is a computer design in which both program instructions and data share the same memory and a single bus, executed sequentially by fetching, decoding, and executing one instruction at a time.","explanation":[{"type":"paragraph","content":"The Von-Neumann Architecture, proposed by John von Neumann, is a stored-program computer model in which both instructions and data are stored together in the same read-write memory, accessed via a single shared bus. The CPU repeatedly performs a fetch-decode-execute cycle, retrieving one instruction from memory at a time, which simplifies design but creates the 'Von-Neumann bottleneck' since the CPU cannot simultaneously fetch an instruction and access data over the shared bus, limiting throughput compared to architectures with separate instruction/data paths (e.g., Harvard architecture)."}]}},{"id":"computer-architecture-2024-5E1780-pA-q5","number":5,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.5. Differentiate between RAM and ROM."}],"answer":{"summary":"RAM (Random Access Memory) is volatile, read-write memory used for temporary program/data storage; ROM (Read Only Memory) is non-volatile memory that permanently stores fixed data/firmware and generally cannot be modified during normal operation.","explanation":[{"type":"paragraph","content":"RAM is volatile read/write memory used for the CPU's working storage of currently executing programs and data, losing its contents when power is removed; it comes in two main types, DRAM (needs periodic refreshing, denser, cheaper) and SRAM (no refresh needed, faster, used for cache). ROM is non-volatile memory that retains its contents without power and is primarily used to store permanent, rarely-changing data such as boot firmware/BIOS; while classic ROM is written once during manufacturing, variants like PROM, EPROM and EEPROM allow limited or field reprogramming, but ROM is still fundamentally read-dominant in normal system operation, unlike RAM's continuous read-write use."}]}},{"id":"computer-architecture-2024-5E1780-pA-q6","number":6,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.6. What is Virtual Memory?"}],"answer":{"summary":"Virtual memory is a memory management technique that gives programs the illusion of a large, contiguous address space by using disk storage to extend physical RAM, with the OS/MMU mapping virtual addresses to physical ones.","explanation":[{"type":"paragraph","content":"Virtual memory is a technique that allows execution of programs whose address space exceeds the size of available physical main memory, by using secondary storage (disk) as an extension of RAM. The operating system, with hardware support from the Memory Management Unit (MMU), divides programs into fixed-size pages (or variable-size segments) and keeps only the currently needed portions in physical memory, transparently swapping pages in and out via page tables that map virtual addresses to physical addresses, giving each process the illusion of a large, private, contiguous address space."}]}},{"id":"computer-architecture-2024-5E1780-pA-q7","number":7,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.7. Mention the various phases in executing an instruction."}],"answer":{"summary":"The phases of instruction execution are: Fetch (retrieve instruction from memory), Decode (interpret opcode and operands), Execute (perform the operation), and Store/Write-back (save the result), often followed by updating the program counter.","explanation":[{"type":"paragraph","content":"The standard instruction execution cycle comprises four principal phases: Fetch, in which the instruction pointed to by the Program Counter (PC) is retrieved from memory into the Instruction Register (IR), and the PC is incremented; Decode, in which the control unit interprets the fetched opcode to determine the operation and identify the operands/addressing mode required; Execute, in which the ALU or other functional unit actually performs the specified operation (arithmetic, logic, memory access, or branch); and Write-back (Store), in which the result of the execution is written back to a register or memory location, completing the cycle before the next instruction fetch begins."}]}},{"id":"computer-architecture-2024-5E1780-pA-q8","number":8,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.8. How overflow occurs in subtraction?"}],"answer":{"summary":"Overflow in subtraction occurs when the result of subtracting two signed numbers exceeds the representable range, typically detected when the carry into the sign bit differs from the carry out of the sign bit.","explanation":[{"type":"paragraph","content":"In signed binary subtraction (performed via addition of the 2's complement), overflow occurs when the mathematical result falls outside the range representable in the fixed number of bits used — for example, subtracting a large negative number from a large positive number can produce a result exceeding the maximum positive value. It is detected in hardware when the carry-in to the most significant (sign) bit differs from the carry-out of that bit (C(in) ≠ C(out)), or equivalently, when the sign of the result is inconsistent with the signs of the operands (e.g., subtracting a negative from a positive yields an apparently negative result), signaling that the true result cannot be correctly represented."}]}},{"id":"computer-architecture-2024-5E1780-pA-q9","number":9,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.9. Distinguish pipelining from parallelism."}],"answer":{"summary":"Pipelining overlaps the execution of multiple instructions across different stages within a single processor for increased throughput, while parallelism uses multiple processors/execution units to simultaneously execute independent instructions or tasks.","explanation":[{"type":"paragraph","content":"Pipelining is a technique within a single processor that overlaps the execution of multiple instructions by dividing instruction processing into sequential stages (fetch, decode, execute, write-back), so that while one instruction is being decoded, the next is being fetched, and so on — improving instruction throughput without requiring multiple processing units. Parallelism, by contrast, involves multiple independent processing units (multiple CPUs, cores, or functional units) executing separate instructions or tasks genuinely simultaneously, as in multiprocessor or multicore systems. Pipelining increases throughput by overlapping stages of sequential execution; parallelism increases throughput by genuinely duplicating execution resources."}]}},{"id":"computer-architecture-2024-5E1780-pA-q10","number":10,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.10. Define segmentation."}],"answer":{"summary":"Segmentation is a memory management technique that divides a program's logical address space into variable-sized, logically meaningful segments (e.g., code, data, stack), each mapped independently to physical memory.","explanation":[{"type":"paragraph","content":"Segmentation is a memory management scheme in which a program's address space is divided into a number of variable-length segments, each corresponding to a logical unit such as the code segment, data segment, or stack segment, rather than fixed-size blocks. Each segment is referenced by a segment number and an offset within that segment, and the system maintains a segment table (with base address and limit/length for each segment) to translate this logical address into a physical memory address, allowing more natural, modular program organization and independent protection/sharing of segments compared to paging."}]}},{"id":"computer-architecture-2024-5E1780-pB-q1","number":1,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.1. Explain Flynn's classification of parallel processing with necessary diagram."}],"answer":{"summary":"Flynn's classification categorizes computer architectures into four classes based on the multiplicity of instruction and data streams: SISD (single processor), SIMD (array/vector processors), MISD (rare, pipelined redundant systems), and MIMD (multiprocessors/multicomputers).","explanation":[{"type":"paragraph","content":"Flynn's classification, proposed by Michael Flynn in 1966, categorizes computer architectures based on the multiplicity of instruction streams and data streams that can be processed simultaneously, yielding four fundamental classes."},{"type":"paragraph","content":"**SISD (Single Instruction, Single Data):** the classical sequential (Von-Neumann) computer, where a single control unit fetches one instruction stream that operates on a single data stream, one operation at a time. Most traditional uniprocessor systems fall into this category, though internal pipelining can still be present."},{"type":"paragraph","content":"**SIMD (Single Instruction, Multiple Data):** a single instruction stream is broadcast to and simultaneously executed by multiple processing elements, each operating on its own distinct data stream. This class includes array processors and vector processors, and is highly efficient for data-parallel tasks like image/signal processing and matrix operations, where the same operation must be applied uniformly across large data sets (modern GPUs extensively use SIMD-style execution)."},{"type":"paragraph","content":"**MISD (Multiple Instruction, Single Data):** multiple processing units each execute a different instruction stream but operate on the same single data stream. This category is rare in practical general-purpose computing and is mainly seen in specialized fault-tolerant systems where multiple processors perform different operations on the same data for redundancy/verification (e.g., systolic arrays or certain space-shuttle flight control computers), or in some pipelined architecture interpretations."},{"type":"paragraph","content":"**MIMD (Multiple Instruction, Multiple Data):** multiple autonomous processors simultaneously execute different instruction streams on different data streams, representing the most general and flexible class. This includes both shared-memory multiprocessors (tightly coupled, common address space) and distributed-memory multicomputers/clusters (loosely coupled, message-passing), and represents the architecture of virtually all modern multicore CPUs and computing clusters."},{"type":"svg","content":""}]}},{"id":"computer-architecture-2024-5E1780-pB-q2","number":2,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.2. Is there any difference between RISC and CISC computers? Explain."}],"answer":{"summary":"RISC (Reduced Instruction Set Computer) uses a small set of simple, fixed-length, single-cycle instructions optimized for pipelining, while CISC (Complex Instruction Set Computer) uses a large set of complex, variable-length, multi-cycle instructions that can directly perform elaborate operations.","explanation":[{"type":"paragraph","content":"Yes, there is a fundamental difference between RISC and CISC computers, rooted in differing design philosophies for the instruction set architecture."},{"type":"paragraph","content":"RISC (Reduced Instruction Set Computer) architectures (e.g., ARM, MIPS, RISC-V) employ a small number of simple instructions, each typically executing in a single clock cycle, with fixed instruction length and a uniform instruction format that simplifies decoding. RISC follows a load-store architecture, meaning only dedicated LOAD and STORE instructions can access memory, while all arithmetic/logic operations work only on registers, and this design is highly amenable to pipelining, resulting in higher clock speeds and instruction throughput, though it may require more instructions to accomplish a complex task and relies heavily on an optimizing compiler."},{"type":"paragraph","content":"CISC (Complex Instruction Set Computer) architectures (e.g., Intel x86) employ a large, rich instruction set including complex, multi-step instructions that can directly perform operations like memory-to-memory arithmetic in a single instruction, with variable instruction length and multiple addressing modes. This reduces the number of instructions needed per program and simplifies compiler design (since more work is done in hardware/microcode), but individual instructions can take multiple clock cycles and the variable-length, complex format makes efficient pipelining considerably harder to implement."},{"type":"list","items":["**Instruction set size:** RISC → small, simple; CISC → large, complex.","**Instruction length:** RISC → fixed; CISC → variable.","**Cycles per instruction:** RISC → mostly 1 cycle; CISC → multiple cycles.","**Memory access:** RISC → load-store only; CISC → direct memory operands allowed.","**Pipelining:** RISC → easy, highly effective; CISC → complex, harder to pipeline efficiently.","**Hardware vs compiler complexity:** RISC → simpler hardware, more compiler optimization; CISC → complex hardware/microcode, simpler compiler."]}]}},{"id":"computer-architecture-2024-5E1780-pB-q3","number":3,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.3. What are addressing modes? Explain each in brief with diagram."}],"answer":{"summary":"Addressing modes specify how the effective operand address is determined from an instruction; common modes include immediate, direct, indirect, register, register indirect, indexed, and relative addressing.","explanation":[{"type":"paragraph","content":"Addressing modes define the rule by which the effective address of an operand is computed from the address field(s) given in an instruction, providing flexibility in how programs reference data."},{"type":"paragraph","content":"**Immediate addressing:** the operand itself is contained directly within the instruction (no memory reference needed), fastest to access but limited to constant values, e.g. `MOV R1, #5`."},{"type":"paragraph","content":"**Direct addressing:** the address field of the instruction directly contains the effective address of the operand in memory, e.g. `MOV R1, [200]` fetches the value stored at memory address 200."},{"type":"paragraph","content":"**Indirect addressing:** the address field contains the address of a memory location which itself holds the effective address of the actual operand (i.e., a pointer), requiring an extra memory access but allowing dynamic addressing."},{"type":"paragraph","content":"**Register addressing:** the operand is held directly in a specified CPU register rather than memory, giving the fastest possible access with no memory reference at all."},{"type":"paragraph","content":"**Register indirect addressing:** the specified register holds the address of the memory location containing the actual operand, combining register speed for address lookup with memory-based data."},{"type":"paragraph","content":"**Indexed addressing:** the effective address is computed by adding the contents of an index register to a constant/base address given in the instruction, useful for accessing array elements."},{"type":"paragraph","content":"**Relative addressing:** the effective address is computed by adding the contents of the Program Counter (PC) to the address field, commonly used for branch/jump instructions to specify a target relative to the current instruction."},{"type":"paragraph","content":"The choice of addressing mode directly affects code density, execution speed, and the flexibility of the instruction set. Modes requiring fewer memory references (immediate, register) execute fastest but offer less flexibility for accessing arbitrary or dynamically computed locations, while modes requiring additional memory references (indirect, indexed) trade some speed for the ability to implement pointers, arrays, and position-independent code. A well-designed instruction set typically provides a mix of these modes so the compiler can select the most efficient one for each specific operand access pattern encountered in a program, such as using indexed addressing for array traversal loops and relative addressing for compact, relocatable branch instructions."},{"type":"svg","content":""}]}},{"id":"computer-architecture-2024-5E1780-pB-q4","number":4,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.4. Describe in detail about the bus arbitration techniques in DMA."}],"answer":{"summary":"Bus arbitration in DMA resolves conflicts when multiple devices request bus access simultaneously; common techniques are daisy chaining (priority by physical position), polling (software-based sequential checking), and independent request/grant lines (centralized/distributed arbitration).","explanation":[{"type":"paragraph","content":"In a system with Direct Memory Access (DMA), multiple devices may simultaneously request control of the system bus to transfer data directly with memory, bypassing the CPU. Bus arbitration is the process/protocol used to determine which requesting device gains control of the bus at any given time, ensuring orderly, conflict-free access."},{"type":"paragraph","content":"**Daisy Chaining:** all devices needing bus access are connected in series, and a single bus-grant signal from the bus controller propagates sequentially through each device in the chain. A device that needs the bus intercepts the grant signal and does not pass it further; otherwise, it passes the signal to the next device. This is simple to implement (requires only one grant line for all devices) but gives fixed, position-based priority (devices closer to the controller get higher priority), and if a device fails, subsequent devices in the chain can be blocked."},{"type":"paragraph","content":"**Polling (software poll):** the bus controller sequentially polls/queries each device (via an address on a set of poll lines) to check if it is requesting the bus, granting access to the first device found requesting it. Priority is determined by the polling sequence programmed by software, offering flexibility to change priority dynamically, but it is slower since multiple polling cycles may be needed before a request is serviced, especially for lower-priority devices."},{"type":"paragraph","content":"**Independent Request/Grant lines (parallel/centralized arbitration):** each device has its own dedicated bus-request and bus-grant line directly connected to a central bus controller (arbiter), which uses fixed or dynamic priority logic to grant access to the highest-priority requester. This is the fastest method since decisions are made in a single step without sequential propagation, but it requires more hardware (dedicated lines per device), making it more expensive to scale to many devices. A related decentralized variant allows each device to independently examine bus-busy status and arbitrate among themselves using shared priority/arbitration lines, avoiding a single central controller bottleneck."}]}},{"id":"computer-architecture-2024-5E1780-pB-q5","number":5,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.5. Describe the procedure for addition and subtraction for fixed point number. Explain with the help of diagram."}],"answer":{"summary":"Fixed-point addition/subtraction of signed numbers is performed using 2's complement representation, where subtraction is implemented as addition of the complemented subtrahend, with overflow detected via carry comparison at the sign bit.","explanation":[{"type":"paragraph","content":"In fixed-point binary arithmetic, numbers are represented in signed 2's complement form to unify addition and subtraction into a single hardware operation. The procedure is as follows."},{"type":"paragraph","content":"**Addition:** the two operands (in 2's complement form, with the sign bit as the most significant bit) are added directly using standard binary addition. Any carry-out beyond the most significant bit is normally discarded (since it represents 'wraparound' in modular 2's complement arithmetic), and the result's sign bit directly indicates the sign of the true result."},{"type":"paragraph","content":"**Subtraction (A − B):** rather than implementing a separate subtractor circuit, subtraction is performed as addition of A and the 2's complement of B, i.e., A + (−B), where −B is obtained by inverting all bits of B and adding 1. This allows the same adder hardware used for addition to also perform subtraction, simplifying the ALU design."},{"type":"paragraph","content":"**Overflow detection:** after the addition (whether from a true add or a subtract-via-complement operation), overflow is detected by comparing the carry into the sign bit (Cn-1) with the carry out of the sign bit (Cn): if these two carries differ (Cn ⊕ Cn-1 = 1), an overflow has occurred, meaning the true mathematical result exceeds the range representable in the given number of bits, and the sign bit of the result cannot be trusted. Equivalently, overflow occurs precisely when both operands have the same sign but the result has a different sign."},{"type":"svg","content":""},{"type":"paragraph","content":"**Worked example:** consider adding two 4-bit signed numbers A = 0111 (+7) and B = 0001 (+1) in 2's complement. Direct binary addition gives 0111 + 0001 = 1000, which as a signed 4-bit number represents −8, an obviously incorrect result since 7+1=8 exceeds the maximum representable positive value (+7) in 4-bit signed format. Checking the carries: the carry into the sign bit (from bit 2 into bit 3) is 1, while the carry out of the sign bit (beyond bit 3) is 0, so Cn ⊕ Cn-1 = 1 ⊕ 0 = 1, correctly flagging an overflow. This same unified adder-based approach, combined with the carry-comparison overflow check, is what allows a single piece of ALU hardware to correctly perform both addition and subtraction of signed fixed-point numbers while reliably detecting the boundary cases where the result cannot be trusted."}]}},{"id":"computer-architecture-2024-5E1780-pB-q6","number":6,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.6. Explain the concept of pipeline in detail."}],"answer":{"summary":"Pipelining divides instruction execution into sequential stages (e.g., fetch, decode, execute, write-back), allowing multiple instructions to be processed concurrently at different stages, increasing throughput analogous to an assembly line.","explanation":[{"type":"paragraph","content":"Pipelining is a technique for implementing instruction-level parallelism within a single processor by overlapping the execution of multiple instructions. The instruction execution process is divided into a sequence of independent stages — commonly Instruction Fetch (IF), Instruction Decode (ID), Execute (EX), Memory Access (MEM), and Write-Back (WB) — each handled by dedicated hardware. While one instruction is in its Execute stage, the next instruction can simultaneously be in its Decode stage, and the one after that in its Fetch stage, much like an assembly line where multiple products are at different stages of completion simultaneously."},{"type":"paragraph","content":"In an ideal k-stage pipeline processing n instructions, once the pipeline is full, one instruction completes every clock cycle rather than every k cycles (as in non-pipelined sequential execution), giving an ideal speedup approaching a factor of k. However, real pipelines suffer from hazards that can stall this ideal throughput: structural hazards (resource conflicts, e.g., two stages needing the same hardware unit simultaneously), data hazards (an instruction depends on the result of a preceding instruction not yet completed, requiring stalls or forwarding/bypassing), and control hazards (branch instructions whose target is not known until later stages, potentially requiring the pipeline to be flushed of incorrectly fetched instructions). Techniques like forwarding, branch prediction, and out-of-order execution are used in modern processors to mitigate these hazards and keep the pipeline as full as possible, maximizing the practical throughput gain from pipelining."},{"type":"paragraph","content":"**Speedup analysis:** for a k-stage pipeline processing n instructions, the total execution time is approximately (k + n − 1) clock cycles, compared to k·n cycles for fully sequential (non-pipelined) execution of the same n instructions. As n grows large, the speedup factor approaches k (the number of pipeline stages), since the fixed pipeline-fill overhead of (k−1) cycles becomes negligible relative to the n cycles of steady-state, one-instruction-per-cycle throughput. This is why modern processors use deep pipelines (often 10-20+ stages) to maximize theoretical throughput, though in practice the achievable speedup is reduced below this ideal by the hazards discussed above, motivating the extensive branch-prediction and hazard-mitigation hardware found in contemporary CPU designs."},{"type":"svg","content":""}]}},{"id":"computer-architecture-2024-5E1780-pB-q7","number":7,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.7. How can we improve the performance of Cache Memory?"}],"answer":{"summary":"Cache performance can be improved by increasing hit ratio through better replacement policies, larger/associative cache, multi-level caching, and write strategies (write-back vs write-through), and by reducing miss penalty through prefetching and larger block sizes.","explanation":[{"type":"paragraph","content":"Cache memory performance is measured chiefly by its hit ratio (fraction of memory accesses satisfied by the cache) and by the miss penalty (extra time needed when data must be fetched from slower main memory). Several strategies improve performance."},{"type":"paragraph","content":"**Improving associativity:** moving from direct-mapped to set-associative or fully-associative cache organization reduces conflict misses (where two frequently used blocks map to the same cache line and repeatedly evict each other), at the cost of more complex, slightly slower hardware for tag comparison."},{"type":"paragraph","content":"**Increasing cache size:** a larger cache can hold more blocks, directly reducing capacity misses, though with diminishing returns and increased cost/access latency beyond a certain size."},{"type":"paragraph","content":"**Multi-level caching (L1, L2, L3):** using a hierarchy of progressively larger, slower cache levels allows a small, very fast L1 cache to handle most requests while a larger L2/L3 cache catches most of the L1 misses before falling back to main memory, balancing speed and capacity."},{"type":"paragraph","content":"**Effective replacement policy:** using an appropriate line-replacement algorithm (e.g., Least Recently Used) when a new block must evict an existing one in a full associative set helps retain the most likely-to-be-reused data, improving the hit ratio."},{"type":"paragraph","content":"**Write policy optimization:** using write-back (updating only the cache on a write, deferring the update to main memory until the block is evicted) instead of write-through (updating main memory on every write) reduces bus traffic and improves performance, though it requires additional dirty-bit tracking for consistency."},{"type":"paragraph","content":"**Block size and prefetching:** choosing an appropriate cache block (line) size exploits spatial locality by bringing in neighboring data on a miss, and hardware/software prefetching can proactively load data expected to be needed soon, both reducing the effective miss penalty experienced by the CPU."}]}},{"id":"computer-architecture-2024-5E1780-pC-q1","number":1,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Q.1. An address space is specified by 24 units and the corresponding memory space by 16 bits:"},{"type":"list","items":["(i) How many words are there in the address space?","(ii) How many words are there in memory space?","(iii) If a page consists of 2k words, how many pages and blocks are there in the system?"]}],"answer":{"summary":"With a 24-bit address space and 16-bit memory space, the address space has 2^24 words, memory space has 2^16 words, and with a page size of 2^k words, there are 2^(24-k) pages and 2^(16-k) blocks.","explanation":[{"type":"paragraph","content":"This is a standard problem in virtual memory organization, relating the size of the logical (virtual) address space to the physical memory space, and to the paging structure."},{"type":"paragraph","content":"**(i) Number of words in the address space:** the address space is specified by 24 bits (units), meaning the logical/virtual address can range over 2^24 distinct addresses. Therefore the address space contains:"},{"type":"math","expression":"2^{24} = 16{,}777{,}216 \\text{ words}","displayMode":true},{"type":"paragraph","content":"**(ii) Number of words in memory space:** the corresponding physical memory space is specified by 16 bits, meaning the physical memory can address 2^16 distinct locations. Therefore the memory space contains:"},{"type":"math","expression":"2^{16} = 65{,}536 \\text{ words}","displayMode":true},{"type":"paragraph","content":"**(iii) Number of pages and blocks:** if each page (in the logical address space) or block (in the physical memory space) consists of 2^k words, the number of pages is found by dividing the total address space by the page size, and the number of blocks is found by dividing the total memory space by the block size:"},{"type":"math","expression":"\\text{Number of pages} = \\dfrac{2^{24}}{2^k} = 2^{24-k}","displayMode":true},{"type":"math","expression":"\\text{Number of blocks} = \\dfrac{2^{16}}{2^k} = 2^{16-k}","displayMode":true},{"type":"paragraph","content":"This illustrates the fundamental relationship in paged virtual memory systems: the logical address is split into a page number field (24-k bits, selecting one of 2^(24-k) pages) and a page offset field (k bits, selecting a word within the page), while the physical address is similarly split into a block number field (16-k bits) and the same offset field (k bits), with the page table performing the mapping from page number to block number for each currently resident page. Since the address space (2^24) is much larger than the memory space (2^16), only a small fraction of the total pages can reside in physical memory at any time, with the remainder held on secondary storage until needed — the essential mechanism that gives virtual memory its ability to run programs larger than physical RAM."},{"type":"paragraph","content":"**Numerical illustration for a specific page size:** if k = 10 (i.e., each page/block holds 2^10 = 1024 words, a common realistic page size), then the number of pages would be 2^(24-10) = 2^14 = 16,384 pages in the address space, while the number of physical blocks would be 2^(16-10) = 2^6 = 64 blocks in memory. This concretely shows the huge disparity between logical and physical capacity in this problem — with only 64 physical page frames available to hold pages from a logical space of 16,384 possible pages, the operating system's page-replacement policy (deciding which resident page to evict when a new page must be brought in) becomes critical to overall system performance, since the vast majority of a program's pages must remain on disk at any given time and be swapped in only as referenced."},{"type":"paragraph","content":"Common page-replacement policies include First-In-First-Out (FIFO, evicting the oldest resident page), Least Recently Used (LRU, evicting the page whose most recent access is furthest in the past, approximating the ideal but requiring tracking overhead), and Optimal (evicting the page that will not be used for the longest time in the future, which requires future knowledge and so serves only as a theoretical benchmark for comparing practical algorithms), each offering different trade-offs between implementation complexity and how closely they approach optimal performance in minimizing page faults."}]}},{"id":"computer-architecture-2024-5E1780-pC-q2","number":2,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Q.2. Explain the following terms with reference to non Von-Neumann Machines:"},{"type":"list","items":["(i) SISD","(ii) SIMD","(iii) MISD","(iv) MIMD"]}],"answer":{"summary":"SISD, SIMD, MISD and MIMD are Flynn's four classes of computer organization based on instruction/data stream multiplicity, ranging from single-processor sequential machines (SISD) to fully parallel multiprocessor systems (MIMD).","explanation":[{"type":"paragraph","content":"These four terms constitute Flynn's taxonomy for classifying non-Von-Neumann (and Von-Neumann) computer organizations based on how many simultaneous instruction streams and data streams the machine can process."},{"type":"paragraph","content":"**(i) SISD (Single Instruction stream, Single Data stream):** represents the classic sequential Von-Neumann computer, where one control unit fetches and executes a single instruction stream operating on a single data stream at any given time. Even though internal techniques like pipelining may be used, only one instruction's logical operation completes conceptually at a time. Most simple, traditional uniprocessor computers belong to this class."},{"type":"paragraph","content":"**(ii) SIMD (Single Instruction stream, Multiple Data streams):** a single control unit issues one instruction that is broadcast to and executed simultaneously by many processing elements, each operating on its own separate data. This organization is highly effective for data-parallel workloads with a regular, uniform computation pattern applied across large arrays of data, such as image processing, matrix/vector arithmetic, and neural network computation — array processors, vector processors, and modern GPU compute cores are practical examples of the SIMD model."},{"type":"paragraph","content":"**(iii) MISD (Multiple Instruction streams, Single Data stream):** multiple processing units, each governed by its own distinct instruction stream, operate on the very same single data stream, typically performing different transformations or checks on that shared data. This organization has very few practical general-purpose implementations and is mainly theoretical or applied in specialized fault-tolerant/redundant computing contexts, where several different algorithms independently validate results computed from the same input data to detect errors, such as in certain aerospace and safety-critical flight-control computer designs."},{"type":"paragraph","content":"**(iv) MIMD (Multiple Instruction streams, Multiple Data streams):** the most general and widely used class today, in which multiple autonomous processors each execute their own independent instruction stream on their own independent data. MIMD systems are further divided into shared-memory multiprocessors, where all processors access a common global memory (requiring cache coherence protocols), and distributed-memory multicomputers/clusters, where each processor has its own local memory and processors communicate via explicit message passing over an interconnection network. Virtually all modern multicore desktop/server CPUs, as well as large-scale computing clusters and supercomputers, are organized as MIMD systems, since it offers maximum flexibility to run different independent programs/tasks concurrently across processors."},{"type":"paragraph","content":"**Comparative summary:** the four classes can be ordered by their degree of parallelism and generality — SISD offers no explicit parallelism at the architectural level and is simplest to program and design; SIMD offers data-level parallelism ideal for regular, uniform computations but is inflexible for irregular or branching workloads (since all active processing elements must execute the same instruction at each step); MISD offers a specialized form of redundant computation on shared data, valuable for reliability but rarely useful for raw performance; and MIMD offers the fullest generality, capable of expressing any combination of task-level and data-level parallelism, at the cost of the most complex hardware (requiring synchronization, cache coherence in shared-memory designs, and communication overhead in distributed designs). This progression from SISD to MIMD broadly traces the historical evolution of computer architecture, from early sequential mainframes through vector supercomputers to today's ubiquitous multicore and cluster-based parallel systems."}]}},{"id":"computer-architecture-2024-5E1780-pC-q3","number":3,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Q.3. Describe various instruction formats and illustrate the same with example."}],"answer":{"summary":"Common instruction formats include three-address, two-address, one-address (accumulator-based), and zero-address (stack-based) formats, differing in how many operand addresses are explicitly specified within the instruction.","explanation":[{"type":"paragraph","content":"An instruction format specifies the layout of an instruction in terms of its constituent fields — typically an opcode field and one or more address fields — and different formats represent different trade-offs between instruction length/complexity and the number of memory/register references required to complete an operation."},{"type":"paragraph","content":"**Three-address instruction format:** the instruction specifies three operand addresses — two source operands and one destination — e.g., `ADD R1, R2, R3` computes R1 = R2 + R3. This format produces compact, efficient programs (fewer total instructions) since a single instruction fully specifies a complete operation, but each instruction itself is longer since it must encode three addresses, increasing instruction word size and hence memory bandwidth requirements for instruction fetch."},{"type":"paragraph","content":"**Two-address instruction format:** the instruction specifies two addresses, where one address serves as both a source operand and the destination (overwriting it), e.g., `ADD R1, R2` computes R1 = R1 + R2. This reduces instruction length compared to three-address format at the cost of destroying one of the original operand values, requiring extra MOV instructions if the original value needs to be preserved."},{"type":"paragraph","content":"**One-address (accumulator-based) instruction format:** the instruction specifies only one explicit address, with the second operand and the destination implicitly being a special CPU register called the accumulator, e.g., `ADD M` computes AC = AC + M[address]. This yields very short instructions but requires the accumulator to be explicitly loaded and stored around each operation via separate LOAD/STORE instructions, increasing the total instruction count for complex expressions."},{"type":"paragraph","content":"**Zero-address (stack-based) instruction format:** the instruction specifies no explicit operand addresses at all; instead, operands are implicitly taken from the top of a push-down stack, and results are pushed back onto the stack, e.g., an ADD instruction pops the top two stack values, adds them, and pushes the result. This requires the operands to be already loaded onto the stack via separate PUSH instructions (converting the expression to postfix/Reverse Polish Notation), producing very compact instructions but a longer overall instruction sequence, and is well suited to expression evaluation and simple compiler code generation."},{"type":"paragraph","content":"**Illustrative example:** evaluating the expression X = (A + B) × (C − D) in each format demonstrates the trade-off: in three-address form, it takes two instructions — `ADD T1, A, B` and `SUB T2, C, D` and `MUL X, T1, T2` (three instructions, each fully specifying its operands); in accumulator (one-address) form, it requires a longer sequence of LOAD/ADD/STORE/LOAD/SUB/STORE/LOAD/MUL/STORE instructions cycling data through the accumulator; and in zero-address (stack) form, the postfix expression `A B + C D − ×` is evaluated using a sequence of PUSH and implicit-operand ADD/SUB/MUL instructions that operate purely on the stack top, illustrating how the same computation requires very different instruction counts and formats depending on the chosen architecture."},{"type":"paragraph","content":"**Design trade-off summary:** the choice of instruction format has direct implications for CPU hardware design and compiler complexity. Formats with more address fields (three-address) require wider instruction words and more complex instruction decoding hardware but minimize total program length and the number of memory/register accesses, generally favored in RISC-style register-rich architectures where instruction fetch bandwidth is cheap relative to register-file access. Formats with fewer address fields (one-address, zero-address) simplify the instruction decoder and reduce instruction word size, historically valuable when memory was expensive and slow, but shift more of the workload onto explicit data-movement instructions, increasing the dynamic instruction count executed per computation. Most modern general-purpose processors adopt a two- or three-address, register-based format as the best practical balance, reserving zero-address (stack) and pure one-address (accumulator) styles for specialized contexts such as expression evaluation in virtual machines (e.g., the Java Virtual Machine uses a stack-based instruction format) or historically simple early computer designs."}]}},{"id":"computer-architecture-2024-5E1780-pC-q4","number":4,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Q.4. Explain with an example about the operations and operands of the computer hardware."}],"answer":{"summary":"Computer hardware operations (arithmetic, logical, shift, transfer, I/O, control) act upon operands (data) held in registers or memory, with the instruction's opcode specifying the operation and its address fields specifying the operand locations.","explanation":[{"type":"paragraph","content":"Every machine instruction fundamentally consists of an operation (specified by the opcode) to be performed upon one or more operands (data values), which may reside in CPU registers, main memory, or be given directly as constants within the instruction."},{"type":"paragraph","content":"**Operations** performed by computer hardware generally fall into several categories: data transfer operations (moving data between registers, memory, and I/O, e.g., LOAD, STORE, MOV), arithmetic operations (ADD, SUB, MUL, DIV, INC, DEC performed by the ALU), logical operations (AND, OR, NOT, XOR performed bitwise on operands), shift operations (logical/arithmetic shifts and rotates, used for fast multiplication/division by powers of two and bit manipulation), and program control operations (branch, jump, call, return, which alter the normal sequential flow of instruction execution based on conditions or unconditionally)."},{"type":"paragraph","content":"**Operands** are the actual data values that operations act upon, and can be specified through the various addressing modes discussed elsewhere in this paper (immediate, direct, indirect, register, indexed, etc.). Operands can be simple scalar values, or can involve more complex data structures such as arrays (accessed via indexed addressing, where an index register combined with a base address selects a specific array element) or pointers (accessed via indirect addressing, where the operand address is itself stored in another location)."},{"type":"paragraph","content":"**Worked example:** consider the instruction `ADD R1, R2, [R3+4]`, computing R1 = R2 + Memory[R3+4]. Here the opcode ADD specifies an arithmetic operation; R1 is the destination operand (using register addressing); R2 is a source operand (also register addressing); and [R3+4] is a source operand using indexed/base-displacement addressing, where the effective memory address is computed by adding the constant displacement 4 to the contents of register R3, and the value fetched from that computed memory location becomes the actual data operand for the addition. This single instruction demonstrates how a single operation (ADD) can simultaneously combine multiple different operand-addressing mechanisms (register-direct and indexed-memory) within one instruction, illustrating the interplay between the operation specified by the opcode and the various ways operands can be located and fetched by the hardware."},{"type":"paragraph","content":"**Data types of operands:** beyond their addressing mode, operands also differ in their underlying data type, which the hardware must correctly interpret to perform the operation — common types include signed/unsigned integers (of varying bit widths, e.g., 8/16/32/64-bit), floating-point numbers (typically IEEE-754 single or double precision, requiring specialized floating-point arithmetic units distinct from the integer ALU), characters/strings (single bytes or sequences thereof, often processed by dedicated string-manipulation instructions in CISC architectures), and Boolean/bit-field data (used by logical and shift operations). The instruction's opcode itself often implicitly encodes the expected operand data type (e.g., separate ADD and FADD opcodes for integer versus floating-point addition), since the hardware circuitry needed to correctly perform an operation differs substantially depending on the operand's representation — this tight coupling between operation and operand type is a key reason why instruction sets typically include multiple variants of arithmetic and comparison instructions, one for each supported data type, rather than a single generic operation."},{"type":"paragraph","content":"This same instruction, `ADD R1, R2, [R3+4]`, can also be contrasted with an equivalent operation written using a different addressing mode to highlight the flexibility operands provide: `ADD R1, R2, #4` would instead add the immediate constant 4 directly to R2 (rather than the value stored at the memory address R3+4), demonstrating that the identical opcode (ADD) combined with different operand-addressing choices produces entirely different computational results, underscoring why both the operation and the precise addressing mode of each operand must be correctly specified for an instruction to behave as the programmer intends."}]}},{"id":"computer-architecture-2024-5E1780-pC-q5","number":5,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Q.5. Write the short notes on the following:"},{"type":"list","items":["(i) Parallel Processing","(ii) Microprogrammed computers","(iii) Associative Memory","(iv) Stacks and Queues","(v) Subroutines"]}],"answer":{"summary":"Parallel processing executes multiple operations simultaneously across multiple units; microprogrammed computers use stored microinstructions to implement the control unit; associative memory is content-addressable; stacks (LIFO) and queues (FIFO) are fundamental linear data structures; subroutines are reusable, callable instruction blocks.","explanation":[{"type":"subheading","content":"(i) Parallel Processing"},{"type":"paragraph","content":"Parallel processing refers to the simultaneous execution of multiple computational tasks or instructions using multiple processing elements, aiming to increase computational speed and throughput beyond what a single sequential processor could achieve. It is realized at multiple levels — instruction-level (pipelining, superscalar execution), data-level (SIMD/vector processing), and task/process-level (multiple cores or processors executing independent programs) — and is essential for high-performance computing applications such as scientific simulation, image processing, and large-scale data analytics, where problems can be decomposed into independent or loosely-coupled sub-computations executed concurrently."},{"type":"subheading","content":"(ii) Microprogrammed computers"},{"type":"paragraph","content":"A microprogrammed computer implements its control unit using a microprogram — a sequence of microinstructions stored in a special control memory (control store) — rather than using fixed, hardwired logic circuits to generate control signals. Each machine-level instruction is decoded to select a corresponding sequence of microinstructions, and each microinstruction directly specifies the micro-operations (register transfers, ALU operations, control signal activations) needed for one step of instruction execution. This approach (introduced by Maurice Wilkes) makes the control unit design more systematic, flexible, and easier to modify or extend (simply by rewriting microcode) compared to hardwired control, at some cost in execution speed due to the extra level of indirection through the control memory."},{"type":"subheading","content":"(iii) Associative Memory"},{"type":"paragraph","content":"Associative memory, also called Content-Addressable Memory (CAM), is a type of memory that is accessed by its content rather than by a specific address. Given a search argument (or a portion of it via a mask register), the memory hardware simultaneously (in parallel) compares the argument against all stored words and returns the address(es)/data of any matching entries, making search operations extremely fast (effectively O(1) regardless of memory size) compared to conventional memory requiring sequential search. It is used in applications requiring very fast lookup, such as cache memory tag comparison, database search acceleration, and network routing tables, though its parallel comparison hardware makes it considerably more expensive per bit than conventional RAM."},{"type":"subheading","content":"(iv) Stacks and Queues"},{"type":"paragraph","content":"A stack is a linear data structure that follows the Last-In-First-Out (LIFO) principle, where elements are inserted (pushed) and removed (popped) only from one end, called the top. Stacks are fundamental to subroutine call/return mechanisms (storing return addresses and local variables in the 'call stack'), expression evaluation (e.g., postfix expression computation), and recursive algorithm implementation. A queue is a linear data structure that follows the First-In-First-Out (FIFO) principle, where elements are inserted (enqueued) at one end (the rear) and removed (dequeued) from the other end (the front), and is commonly used for buffering tasks such as I/O device request handling, process scheduling, and any scenario requiring elements to be processed strictly in the order they arrived."},{"type":"subheading","content":"(v) Subroutines"},{"type":"paragraph","content":"A subroutine (or procedure/function) is a self-contained, reusable block of instructions designed to perform a specific, well-defined task, which can be invoked (called) from multiple points within a program without duplicating its code. When a CALL instruction is executed, the return address (the address of the instruction following the call) is saved, typically by pushing it onto the stack, and control transfers to the subroutine's starting address; upon completion, a RETURN instruction pops the saved return address from the stack and transfers control back to the calling program, resuming execution exactly where it left off. This mechanism supports modular program design, code reuse, and (via the stack-based storage of return addresses and parameters) enables recursive subroutine calls."}]}}],"examYear":2024},{"id":"computer-architecture-2022-5E1391","title":"Computer Architecture (2022)","subjectSlug":"computer-architecture","subjectName":"Computer Architecture","universitySlug":"rtu","branchSlug":"ee-ec-eee","year":3,"semester":5,"paperCode":"5E1391","questions":[{"id":"computer-architecture-2022-5E1391-pA-q1","number":1,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.1. What is virtual memory?"}],"answer":{"summary":"Virtual memory is a memory management technique using secondary storage to extend the apparent size of main memory, giving each program the illusion of a large, contiguous address space managed transparently by the OS and MMU.","explanation":[{"type":"paragraph","content":"Virtual memory allows a program to execute even if its address space is larger than physical RAM, by keeping only actively used portions (pages/segments) in main memory and holding the rest on disk, with the OS and Memory Management Unit transparently handling address translation and swapping, giving each process the appearance of a large, private, contiguous memory space regardless of actual physical memory constraints."}]}},{"id":"computer-architecture-2022-5E1391-pA-q2","number":2,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.2. What is meant by an interleaved memory?"}],"answer":{"summary":"Interleaved memory divides memory into multiple independently-accessible banks so consecutive addresses lie in different banks, allowing overlapped/simultaneous access to increase effective memory bandwidth.","explanation":[{"type":"paragraph","content":"Interleaved memory is an organization in which main memory is divided into several independent modules or banks, with consecutive memory addresses distributed cyclically across these banks (e.g., address 0 in bank 0, address 1 in bank 1, address 2 in bank 2, and so on). This allows the memory controller to initiate an access to the next bank before the previous bank's access has completed, effectively overlapping multiple memory accesses in a pipelined fashion, which significantly increases effective memory bandwidth and reduces the average memory access time as seen by the CPU, particularly beneficial for sequential/block memory accesses common in instruction fetching and array processing."}]}},{"id":"computer-architecture-2022-5E1391-pA-q3","number":3,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.3. Define segmentation."}],"answer":{"summary":"Segmentation divides a program's logical address space into variable-sized, logically meaningful segments (code, data, stack), each independently addressed via a segment number and offset.","explanation":[{"type":"paragraph","content":"Segmentation is a memory management technique that partitions a program into variable-length logical units called segments (such as the code segment, data segment, and stack segment), each treated as a separate independent entity with its own base address and length maintained in a segment table. An address in a segmented system consists of a segment number and an offset within that segment, allowing modular program organization, independent protection and sharing of segments, and better correspondence to the logical structure of a program compared to fixed-size paging."}]}},{"id":"computer-architecture-2022-5E1391-pA-q4","number":4,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.4. Explain input-output processor."}],"answer":{"summary":"An input-output processor (IOP) is a dedicated processor that autonomously manages I/O data transfers between peripherals and memory, executing its own I/O channel programs independently of the main CPU.","explanation":[{"type":"paragraph","content":"An Input-Output Processor is a specialized processing unit that offloads the task of managing peripheral I/O operations from the main CPU, executing its own instruction set (I/O or channel programs) to control data transfer, formatting, and error checking between I/O devices and main memory. Once initiated by the CPU with a starting instruction, the IOP operates independently and only interrupts the CPU when the entire I/O task is complete, allowing the CPU to perform other computation concurrently and significantly improving overall system efficiency in I/O-intensive environments."}]}},{"id":"computer-architecture-2022-5E1391-pA-q5","number":5,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Q.5. Write the rules to perform addition of floating point numbers."}],"answer":{"summary":"Floating-point addition requires aligning the exponents of both operands (by shifting the smaller-exponent mantissa right), adding the aligned mantissas, then normalizing and rounding the result.","explanation":[{"type":"paragraph","content":"The rules for adding two floating-point numbers are: (1) compare the exponents of the two numbers, and if they differ, shift the mantissa of the number with the smaller exponent to the right by the difference in exponents, so both numbers share the same (larger) exponent, a step called alignment; (2) add the two aligned mantissas using standard fixed-point addition; (3) normalize the resulting mantissa if needed, so it falls within the standard normalized range (e.g., 1.xxxx for IEEE format), adjusting the exponent accordingly if the addition produced a carry-out or a leading-zero mantissa; and (4) round the final normalized result to fit the available mantissa bit-width, checking for overflow/underflow in the exponent range."}]}},{"id":"computer-architecture-2022-5E1391-pB-q1","number":1,"marks":10,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.1. What are the addressing modes? Explain each in brief with diagram."}],"answer":{"summary":"Addressing modes (immediate, direct, indirect, register, register indirect, indexed, relative) define how an instruction's address field is interpreted to locate the actual operand, trading off flexibility, instruction length, and access speed.","explanation":[{"type":"paragraph","content":"Addressing modes specify the method by which the effective address of an operand referenced by an instruction is determined, providing a range of options that trade off flexibility, code compactness, and access speed."},{"type":"paragraph","content":"**Immediate addressing:** the operand value is embedded directly within the instruction itself, requiring no additional memory access to fetch it; used for specifying constants, e.g. `MOV R1, #10` loads the literal value 10 into R1."},{"type":"paragraph","content":"**Direct addressing:** the instruction's address field contains the actual memory address of the operand directly, e.g. `MOV R1, 500` loads the value stored at memory address 500 into R1; simple but limited by the address field's bit-width to a fixed range of directly addressable memory."},{"type":"paragraph","content":"**Indirect addressing:** the address field contains the address of a memory location that itself holds the effective address of the operand (a pointer to a pointer, conceptually), requiring two memory accesses — one to fetch the address, one to fetch the actual data — but enabling powerful dynamic addressing useful for pointers and linked data structures."},{"type":"paragraph","content":"**Register addressing:** the operand resides directly in a named CPU register, offering the fastest possible access since no memory reference is needed at all, though limited by the small number of available registers."},{"type":"paragraph","content":"**Register indirect addressing:** the named register holds the memory address of the actual operand rather than the operand itself, combining fast register-based address lookup with the larger addressable range of memory."},{"type":"paragraph","content":"**Indexed addressing:** the effective address is computed by adding the content of a designated index register to a base address/displacement specified in the instruction, which is especially useful for accessing successive elements of an array by simply incrementing the index register between accesses."},{"type":"paragraph","content":"**Relative addressing:** the effective address is computed by adding the content of the Program Counter to an offset specified in the instruction, predominantly used for branch and jump instructions so that program code can be relocated in memory without needing to modify absolute jump targets."},{"type":"paragraph","content":"**Selecting an addressing mode in practice:** a compiler generating machine code chooses among these modes based on the nature of the data being accessed — constants are compiled using immediate addressing, simple scalar global variables often use direct addressing, pointer dereferencing in high-level languages naturally maps to indirect or register-indirect addressing, array/structure element access maps to indexed addressing, and control-flow constructs (if/while/for loops, function calls) map to relative addressing for their branch targets. Since real programs use all of these access patterns extensively, providing a rich set of addressing modes in the instruction set architecture allows the compiler to generate more compact and efficient code than would be possible with only one or two addressing modes, though at the cost of more complex instruction decoding hardware in the CPU."},{"type":"paragraph","content":"**Hardware cost consideration:** each additional addressing mode supported by an ISA requires corresponding decoder logic and, in some cases, extra address-computation hardware (adders for indexed/relative modes, additional memory-access cycles for indirect modes), so architects must balance the code-density and flexibility benefits of a rich addressing-mode set against the resulting increase in CPU control-unit complexity and, for indirect/indexed modes, the extra clock cycles needed to compute the effective address before the actual operand can be fetched."},{"type":"svg","content":""}]}},{"id":"computer-architecture-2022-5E1391-pB-q2","number":2,"marks":10,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.2. Describe in detail about the bus arbitration techniques in DMA."}],"answer":{"summary":"Bus arbitration techniques in DMA — daisy chaining, polling, and independent request/grant lines — determine which of multiple simultaneously-requesting DMA devices gains control of the shared system bus.","explanation":[{"type":"paragraph","content":"When multiple DMA-capable devices may need to access the system bus to transfer data with memory independently of the CPU, bus arbitration mechanisms determine which device is granted control at any moment, since only one device can drive the bus at a time."},{"type":"paragraph","content":"**Daisy Chaining:** devices are connected in a series (chain) with respect to a single bus-grant signal originating from the bus controller. When a device requests the bus, it examines the incoming grant signal; if it needs the bus, it takes control and blocks the signal from propagating further; otherwise, it passes the grant signal on to the next device in the chain. Priority is thus fixed by physical position (devices earlier in the chain, closer to the controller, always have higher priority), which is simple and requires minimal wiring but is inflexible and vulnerable to a single device failure disrupting the entire chain."},{"type":"paragraph","content":"**Polling:** the bus controller sequentially interrogates each device (using a set of address/poll lines) to determine which one is requesting bus access, granting the bus to the first device found to be requesting it in the polling sequence. This method allows software to dynamically alter device priority simply by changing the polling order/program, offering greater flexibility than fixed daisy chaining, but is comparatively slower since it may require several polling cycles before reaching and servicing a lower-priority device's request."},{"type":"paragraph","content":"**Independent Request/Grant (centralized parallel arbitration):** each device is connected to the bus controller via its own dedicated request and grant line, allowing the controller to receive all requests simultaneously and use built-in priority-encoding logic to immediately grant the bus to the highest-priority requester in a single decision step. This offers the fastest arbitration response since there is no sequential propagation delay (as in daisy chaining) or repeated polling cycles, but requires significantly more wiring/hardware, scaling less economically as the number of devices grows large."},{"type":"paragraph","content":"**Cost/speed comparison:** daisy chaining requires the least wiring (a single grant line threaded through all devices) but is the slowest to resolve arbitration for devices far down the chain and offers no priority flexibility; polling requires moderate wiring (a set of address lines shared by all devices) and offers software-configurable priority at the cost of potentially several polling cycles' delay; and independent request/grant lines offer the fastest, single-step arbitration decision but scale poorly in wiring cost as the number of devices grows, since each device needs its own dedicated pair of lines to the central arbiter. **Priority schemes within arbitration:** regardless of which physical arbitration technique is used, the system must also define a priority policy for resolving simultaneous requests. Fixed (static) priority always favors the same device(s) in case of conflict, which is simple but can lead to starvation of low-priority devices under heavy contention from high-priority ones. Rotating (round-robin) priority cycles which device is considered highest priority after each grant, ensuring fairer long-term access distribution among devices. The choice of arbitration technique combined with the priority scheme is an important system design decision, balancing hardware cost, arbitration speed, and fairness of access among competing DMA-capable devices such as disk controllers, network interfaces, and graphics adapters."}]}},{"id":"computer-architecture-2022-5E1391-pB-q3","number":3,"marks":10,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.3. What are the 3 different cache memory schemes? Explain in detail."}],"answer":{"summary":"The three main cache mapping schemes are direct mapping (each memory block maps to exactly one cache line), fully associative mapping (any block can go in any cache line), and set-associative mapping (a hybrid where each block maps to a specific set containing multiple lines).","explanation":[{"type":"paragraph","content":"Cache mapping schemes define the rule by which a block of main memory is placed into, and subsequently located within, the cache."},{"type":"paragraph","content":"**Direct Mapping:** each main memory block can be placed in only one specific, predetermined cache line, calculated typically as (block address) MOD (number of cache lines). The memory address is divided into a tag field, a line/index field (identifying the specific cache line), and a word/offset field (identifying the word within the block). On access, the hardware simply indexes directly to the corresponding cache line and compares the stored tag with the incoming address's tag to check for a hit. This scheme is simple and fast to implement (no search required) but suffers from a high conflict-miss rate when multiple frequently used blocks map to the same line and repeatedly evict one another, even if other cache lines are free."},{"type":"paragraph","content":"**Fully Associative Mapping:** a memory block can be placed in any available cache line whatsoever, with no fixed mapping rule. The memory address is divided only into a tag field and a word/offset field (no line/index field is needed). On access, the hardware must simultaneously compare the incoming tag against the tags of all cache lines in parallel (using comparator hardware for each line) to determine a hit. This scheme offers maximum flexibility and the lowest possible conflict-miss rate for a given cache size, but requires expensive, complex parallel-comparison hardware that becomes impractical for large caches."},{"type":"paragraph","content":"**Set-Associative Mapping:** a compromise between the two extremes, in which the cache is divided into a number of sets, each containing a small number of lines (e.g., a 4-way set-associative cache has sets of 4 lines each), and a given memory block maps to exactly one specific set (via a modulo calculation on the set index field) but can occupy any of the lines within that set. The memory address is divided into a tag field, a set-index field, and a word/offset field. On access, the hardware indexes to the correct set and then compares the tag against only the (small number of) lines within that set in parallel, balancing the simplicity/speed of direct mapping with much of the reduced-conflict benefit of full associativity, making it the mapping scheme most commonly used in real-world processor cache designs (typical values are 2-way, 4-way, or 8-way set-associative)."},{"type":"paragraph","content":"**Comparative trade-off:** as associativity increases from direct-mapped (equivalent to 1-way set-associative) toward fully associative (where the entire cache is a single set), the conflict-miss rate decreases since a block has more candidate locations to occupy without evicting another actively-used block, but the hardware cost, access latency, and power consumption of the parallel tag-comparison logic increase correspondingly. Empirical studies of real workloads generally show diminishing returns beyond 4-way or 8-way associativity, which is why most modern processor caches settle on these values as the practical sweet spot between direct-mapped simplicity/speed and fully-associative flexibility, reserving fully associative designs mainly for very small structures like the Translation Lookaside Buffer (TLB), where the total number of entries is small enough that full parallel comparison remains hardware-feasible."}]}},{"id":"computer-architecture-2022-5E1391-pB-q4","number":4,"marks":10,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.4. What are the various modes of data transfer to and from the computer system? Explain."}],"answer":{"summary":"Data transfer to/from a computer system occurs via three main modes: Programmed I/O (CPU actively polls/transfers each data item), Interrupt-driven I/O (device signals the CPU when ready, allowing other work in between), and DMA (Direct Memory Access, where a dedicated controller transfers blocks of data directly to/from memory without CPU involvement).","explanation":[{"type":"paragraph","content":"There are three principal modes by which data is transferred between I/O devices and main memory (or CPU registers), differing significantly in how much direct CPU involvement is required."},{"type":"paragraph","content":"**Programmed I/O:** the CPU itself is fully responsible for supervising and executing every data transfer, continuously polling (checking) a status flag/register of the I/O device to determine when it is ready to send or receive the next data item, then executing an explicit instruction to move that single data item between the device and a CPU register or memory. This is simple to implement in software but extremely wasteful of CPU time, since the processor is kept in a busy-wait loop, unable to perform any other useful work, for the entire (often slow, relative to CPU speed) duration of each I/O operation."},{"type":"paragraph","content":"**Interrupt-driven I/O:** rather than continuously polling, the CPU issues an I/O command and then proceeds to execute other, unrelated instructions/programs. When the I/O device becomes ready to transfer data, it raises an interrupt signal to the CPU, which then temporarily suspends its current task, executes a dedicated interrupt-service routine to perform the actual data transfer for that one data item, and then resumes its previous task. This frees the CPU from busy-waiting and allows useful overlap of computation with I/O, though the CPU is still directly involved in transferring every individual data item (just not continuously polling for readiness), and each interrupt incurs some processing overhead (context saving/restoring)."},{"type":"paragraph","content":"**Direct Memory Access (DMA):** a specialized DMA controller hardware is given the source/destination addresses and the total block size for an entire transfer by the CPU, and then autonomously manages the transfer of an entire block of data directly between the I/O device and main memory, without requiring the CPU to be involved in moving each individual data item. The DMA controller briefly takes control of the system bus (cycle-stealing from the CPU as needed) to perform each word transfer, and only interrupts the CPU once at the very end, when the entire block transfer is complete. This is by far the most efficient mode for large data transfers (such as disk or high-speed network I/O), since it minimizes CPU involvement to only initiating and being notified of completion, freeing the CPU to perform substantial computation concurrently with the ongoing I/O transfer."},{"type":"paragraph","content":"**Comparative summary and typical usage:** these three modes represent a progression of decreasing CPU involvement and increasing hardware complexity. Programmed I/O is appropriate only for very simple systems or slow, infrequent I/O operations where the CPU has nothing else useful to do (e.g., a basic embedded controller polling a single sensor). Interrupt-driven I/O is well suited to moderate-speed, character-oriented devices such as keyboards and mice, where individual data items arrive relatively infrequently and the overhead of an interrupt for each item is acceptable. DMA is essential for high-speed, block-oriented devices such as disk drives, network interfaces, and graphics frame buffers, where the sheer volume of data would overwhelm the CPU if handled item-by-item via polling or interrupts; virtually all modern general-purpose computer systems rely on DMA for disk and network I/O specifically because of the enormous CPU-time savings it provides for these high-throughput transfer scenarios."}]}},{"id":"computer-architecture-2022-5E1391-pB-q5","number":5,"marks":10,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.5. Explain Flynn's classification with suitable examples."}],"answer":{"summary":"Flynn's classification (SISD, SIMD, MISD, MIMD) categorizes computers by instruction/data stream multiplicity: SISD is a standard uniprocessor, SIMD applies one instruction across many data elements (e.g., GPUs), MISD is a rare redundant/fault-tolerant design, and MIMD covers general multiprocessors/clusters.","explanation":[{"type":"paragraph","content":"Flynn's classification scheme organizes computer architectures into four categories based on whether the machine can process single or multiple instruction streams, and single or multiple data streams, simultaneously."},{"type":"paragraph","content":"**SISD (Single Instruction, Single Data):** the conventional sequential computer, exemplified by a basic single-core processor executing a traditional program — one instruction is fetched and executed on one data item at a time by a single control unit and single processing unit, e.g. an old-generation single-core desktop CPU running a simple program without any internal parallel execution units."},{"type":"paragraph","content":"**SIMD (Single Instruction, Multiple Data):** one control unit broadcasts a single instruction simultaneously to multiple processing elements, each of which applies that same operation to its own distinct data element in lock-step. A canonical example is adding two large arrays element-by-element: a SIMD machine can perform many of the additions simultaneously in a single instruction cycle, rather than looping through elements sequentially. Modern GPU compute cores and CPU vector extensions (such as AVX/SSE 'single instruction, multiple data' instructions used for multimedia and scientific computation) are practical, widely-deployed examples of the SIMD model."},{"type":"paragraph","content":"**MISD (Multiple Instruction, Single Data):** multiple processing units, each executing a different instruction stream, all operate upon the identical single data stream. This is the rarest and least commercially implemented class; a conceptual example is a fault-tolerant flight-control system where several processors, each running a differently-implemented algorithm, independently process the very same sensor data stream, and their results are cross-checked/voted upon to detect hardware or software errors — used in some space-shuttle and safety-critical avionics computer designs, though no significant general-purpose commercial computer uses this model."},{"type":"paragraph","content":"These four classes are frequently visualized on a simple two-by-two grid, with instruction-stream multiplicity (single/multiple) on one axis and data-stream multiplicity (single/multiple) on the other, making it easy to see how each class represents one specific combination of these two independent design dimensions."},{"type":"paragraph","content":"**MIMD (Multiple Instruction, Multiple Data):** multiple independent processors, each with its own instruction stream, operate on their own independent data streams, representing the most general and now-dominant class of parallel computer. An example is a modern multicore server or a computing cluster, where different cores/nodes can simultaneously execute entirely different programs (or different parts of the same parallel program) on different data — MIMD systems are further subdivided into shared-memory multiprocessors (e.g., a typical multicore desktop CPU with cores sharing a common RAM) and distributed-memory multicomputers/clusters (e.g., a supercomputer or cloud-computing cluster where each node has private memory and nodes communicate via message passing over a network)."},{"type":"paragraph","content":"**Practical significance of the classification:** Flynn's taxonomy remains valuable today primarily as a conceptual framework for reasoning about how a given algorithm's structure should be matched to appropriate hardware — a data-parallel algorithm with a uniform, regular computation pattern (such as applying the same filter to every pixel of an image) is naturally suited to SIMD hardware for maximum efficiency, while an algorithm composed of genuinely independent, heterogeneous sub-tasks (such as running a web server alongside a database alongside a background batch job) is naturally suited to MIMD hardware. Understanding this classification helps both hardware architects design appropriately specialized processing units and software developers choose the right parallelization strategy (vectorization for SIMD-friendly code versus multithreading/multiprocessing for MIMD-friendly code) for their specific computational problem."}]}},{"id":"computer-architecture-2022-5E1391-pB-q6","number":6,"marks":10,"tags":["Part B"],"text":[{"type":"paragraph","content":"Q.6. What is the difference between cache memory & associative memory? Explain in detail."}],"answer":{"summary":"Cache memory is a small, fast buffer holding recently/frequently used data based on locality of reference and accessed via direct/set-associative mapping using a tag comparison, while associative memory is content-addressable, searched in parallel by data content rather than address, used for fast lookup applications beyond just caching.","explanation":[{"type":"paragraph","content":"Although cache memory is very often internally implemented using associative (or set-associative) search techniques, the two terms refer to conceptually distinct ideas, and it is important to distinguish the general concept of 'associative memory' as a content-addressable storage mechanism from 'cache memory' as a specific application of fast, small memory that sits between CPU and main memory to exploit locality of reference."},{"type":"paragraph","content":"**Purpose and role:** cache memory's specific purpose is to reduce the average time the CPU spends waiting for memory access, by holding copies of recently/frequently accessed instructions and data closer to the processor, based on the principle of locality of reference (temporal locality — recently accessed data is likely to be accessed again soon; spatial locality — data near recently accessed addresses is likely to be accessed soon). Associative memory's purpose is more general: it is any memory that is accessed and searched by matching content (a search key/argument) rather than by a numeric address, and is used wherever extremely fast content-based lookup is needed, such as in cache tag comparison, but also in database indexing, network routers' routing tables, and pattern-matching hardware, independent of any specific relationship to a 'main memory hierarchy'."},{"type":"paragraph","content":"**Addressing mechanism:** cache memory (particularly in direct-mapped or set-associative configurations, the most common in practice) is still fundamentally accessed using a portion of the memory address (an index field selects a line or set, and a tag field is then compared to verify a hit) — it is not necessarily searched purely by content across the entire structure. Associative memory, in its pure/fully-associative form, is searched by presenting a data pattern (with an optional mask to ignore certain bit positions) and having all memory words compared to that pattern simultaneously in parallel hardware, returning the address or contents of any matching word(s), entirely independent of any specific address indexing scheme."},{"type":"paragraph","content":"**Relationship:** a fully-associative cache is, in fact, an application of true associative memory technology specifically used to implement a cache, meaning associative memory is the broader, more general hardware concept, while (fully-associative) cache memory is one particular, very common application of that concept, specialized specifically for the task of speeding up CPU-to-main-memory access. Direct-mapped and set-associative caches, by contrast, use only partial associative (parallel tag comparison within a set) search rather than the full parallel search across the entire memory, representing a design trade-off between the search speed/flexibility benefits of associative memory and the higher hardware cost that fully associative search entails at large capacities."},{"type":"paragraph","content":"**Cost and scalability implications:** because fully associative (pure content-addressable) memory requires a dedicated comparator circuit for every single storage location to enable true parallel search, its hardware cost per bit is substantially higher than conventional address-indexed memory, and this cost grows roughly linearly with capacity — making pure associative memory practical only for small structures (such as a modestly-sized fully-associative cache, a TLB, or specialized network routing hardware) rather than for large-capacity general storage. This is precisely why large modern caches (which may hold megabytes of data) are built as set-associative rather than fully associative structures: the set-associative design captures most of the conflict-miss reduction benefit of full associativity while requiring parallel comparison only within each small set (typically 4 to 16 lines) rather than across the entire cache, keeping the associative-search hardware cost manageable even as total cache capacity scales into the megabyte range."}]}},{"id":"computer-architecture-2022-5E1391-pC-q1","number":1,"marks":15,"tags":["Part C"],"text":[{"type":"paragraph","content":"Q.1. Describe different instruction formats and illustrate the same with an example."}],"answer":{"summary":"Instruction formats — three-address, two-address, one-address (accumulator), and zero-address (stack) — differ in how many explicit operand addresses are encoded, trading off instruction length against total instruction count for a given computation.","explanation":[{"type":"paragraph","content":"An instruction format defines the structural layout of a machine instruction, consisting of an opcode field specifying the operation, and zero or more address fields specifying the location of operands and results. Different numbers of address fields lead to fundamentally different program styles and hardware requirements."},{"type":"paragraph","content":"**Three-address format:** specifies two source operand addresses and one destination address explicitly, e.g. `ADD R1, R2, R3` performs R1 ← R2 + R3. This allows each instruction to fully and independently specify a complete operation without disturbing either source operand, minimizing the total number of instructions needed for a complex expression, at the cost of longer individual instruction words (since three full addresses must be encoded)."},{"type":"paragraph","content":"**Two-address format:** specifies two addresses, where the first typically serves as both a source operand and the destination, e.g. `ADD R1, R2` performs R1 ← R1 + R2, overwriting the original value in R1. This shortens instruction length relative to three-address format but destroys one operand's original value, sometimes requiring an extra register-copy instruction beforehand if that value is still needed."},{"type":"paragraph","content":"**One-address (accumulator) format:** specifies only a single explicit address, with the second implicit operand and the result both associated with a special accumulator register, e.g. `ADD M` performs AC ← AC + Memory[M]. This produces the shortest individual instructions among the register/memory-addressed formats, but requires separate LOAD and STORE instructions to move values into and out of the accumulator around each operation, increasing the total instruction count for any expression involving more than one operation."},{"type":"paragraph","content":"**Zero-address (stack) format:** specifies no explicit operand address at all; all operations implicitly act on the top element(s) of a push-down stack, e.g. an ADD instruction pops the top two values from the stack, adds them, and pushes the result back. Programs for a stack machine are naturally expressed in postfix (Reverse Polish) notation and require explicit PUSH instructions to load operands onto the stack before each operation, yielding the shortest instructions of all formats but often the longest overall instruction sequences."},{"type":"paragraph","content":"**Illustrative example — evaluating X = (A + B) × C:** In three-address format, this takes two instructions: `ADD T, A, B` (T ← A+B) followed by `MUL X, T, C` (X ← T×C). In two-address format: `MOV R1, A` then `ADD R1, B` then `MUL R1, C` then `MOV X, R1` — four instructions since each two-address instruction can only update one operand in place. In one-address (accumulator) format: `LOAD A`, `ADD B`, `MUL C`, `STORE X` — four instructions, cycling every value through the single accumulator. In zero-address (stack) format, using the postfix expression `A B + C ×`: `PUSH A`, `PUSH B`, `ADD` (pops A,B, pushes A+B), `PUSH C`, `MUL` (pops sum and C, pushes result), `POP X` — six instructions, demonstrating that while each individual stack instruction is minimal (no address field), the total instruction count is typically the highest among the four formats for equivalent computations."},{"type":"paragraph","content":"**A second worked example — evaluating Y = (A − B) / (C + D × E), a more complex expression involving four operations:** In three-address format, this requires four instructions, each computing one sub-expression into a temporary: `MUL T1, D, E` (T1 ← D×E), `ADD T2, C, T1` (T2 ← C+T1), `SUB T3, A, B` (T3 ← A−B), and `DIV Y, T3, T2` (Y ← T3/T2) — exactly one instruction per operation in the expression tree, since three-address instructions never need to reload an operand that was just computed. In one-address (accumulator) format, the same expression requires careful sequencing since the accumulator can only hold one intermediate value at a time, and any value that must be combined with a later result needs to be explicitly stored to memory and reloaded: `LOAD D`, `MUL E` (AC = D×E), `ADD C` (AC = C+D×E), `STORE T` (save denominator), `LOAD A`, `SUB B` (AC = A−B), then a division instruction combining AC with the stored T, followed by `STORE Y` — around eight instructions, nearly double the three-address count, illustrating how the single-accumulator bottleneck increasingly penalizes more complex, multi-operand expressions as their structure deepens."},{"type":"paragraph","content":"**Register-rich RISC extension of two-address format:** modern RISC architectures typically extend the two-address concept into an effectively three-address, register-only format (since they have a large general-purpose register file rather than a single accumulator), combined with a strict load-store discipline where only dedicated LOAD and STORE instructions may reference memory, and all arithmetic instructions operate purely on registers. This hybrid design captures the instruction-count efficiency of three-address addressing (each arithmetic instruction fully specifies its operation without destroying an input) while keeping individual instructions short and uniformly formatted (since register numbers require far fewer bits to encode than full memory addresses), which is a major reason why the three-address, register-based instruction format dominates contemporary general-purpose processor design, from ARM and RISC-V embedded/mobile processors to the internal micro-operation format used even inside modern x86 CISC processors after their front-end instruction decoders translate complex CISC instructions into simpler RISC-like internal operations."},{"type":"paragraph","content":"**Illustrating with an instruction word diagram:** a typical three-address register instruction might allocate, say, 6 bits for the opcode and 5 bits for each of three register fields (supporting up to 32 registers), for a total instruction width of 21 bits, comfortably fitting within a standard 32-bit fixed instruction word with room to spare for future extension (e.g., for larger immediate-value fields or additional opcode variants as the instruction set evolves). By contrast, a one-address memory-referencing instruction on the same machine might need 6 bits for the opcode plus a full 16-24 bit memory address field just to reference one operand, illustrating why accumulator-based one-address designs were historically favored when memory address buses were narrow and instruction words needed to stay compact, while today's wide instruction words and abundant registers make the three-address, register-only format the clearly preferable choice for general-purpose computing."},{"type":"paragraph","content":"**Conclusion:** the historical progression from zero-address and one-address machines (in the earliest computers, constrained by expensive, scarce memory and minimal register hardware) through two-address designs and finally to today's dominant three-address register-based RISC format directly reflects the changing economics of computer hardware over the decades — as transistor budgets grew and register files became cheap and abundant, instruction formats evolved to exploit that abundance for maximum performance, a trend that instruction set architecture designers continue to navigate today when balancing code density, decode complexity, and execution throughput for new processor generations."}]}},{"id":"computer-architecture-2022-5E1391-pC-q2","number":2,"marks":15,"tags":["Part C"],"text":[{"type":"paragraph","content":"Q.2. Describe in detail about the memory technologies."}],"answer":{"summary":"Memory technologies span the hierarchy from fast, volatile, expensive registers and SRAM cache through DRAM main memory, to slower, non-volatile, cheaper secondary storage (magnetic disk, SSD) and ROM/EEPROM-based firmware storage, each offering different speed-cost-capacity-volatility trade-offs.","explanation":[{"type":"paragraph","content":"Computer memory technologies span a hierarchy characterized by trade-offs between speed, cost per bit, storage capacity, and volatility (whether contents are retained without power)."},{"type":"paragraph","content":"**Registers:** the fastest memory technology, implemented directly within the CPU using flip-flops, offering access times comparable to the processor's clock cycle, but extremely limited in number/capacity (a few dozen to a few hundred registers) and the most expensive per bit."},{"type":"paragraph","content":"**SRAM (Static RAM):** used for cache memory, SRAM stores each bit using a bistable flip-flop circuit (typically six transistors), requiring no periodic refresh and offering very fast access times (a few nanoseconds), but consuming more chip area and power per bit than DRAM, making it costlier and used only where speed is paramount (L1/L2/L3 caches)."},{"type":"paragraph","content":"**DRAM (Dynamic RAM):** used for main memory, DRAM stores each bit as a charge on a tiny capacitor (using a single transistor per cell), making it much denser and cheaper per bit than SRAM, but the capacitor charge leaks over time, requiring periodic refresh circuitry to rewrite the data, and access is somewhat slower than SRAM. Variants like SDRAM, DDR, DDR2/3/4/5 SDRAM are synchronized with the system clock and pipeline multiple accesses to increase effective bandwidth for main memory use."},{"type":"paragraph","content":"**ROM (Read-Only Memory) and its variants:** ROM is a non-volatile memory technology (retains data without power) whose contents are typically fixed at manufacture (mask ROM) or, in more flexible variants, can be programmed and in some cases reprogrammed: PROM can be electrically programmed once by the user; EPROM can be erased using ultraviolet light and reprogrammed; and EEPROM (and its descendant, flash memory) can be electrically erased and reprogrammed in-circuit, without special equipment, making it the basis of modern firmware storage, USB drives, and SSD storage cells."},{"type":"paragraph","content":"**Secondary/auxiliary storage:** magnetic disk (hard disk drives) and solid-state drives (SSDs, built from flash memory/EEPROM technology) provide much larger capacity at much lower cost per bit than main memory, but with significantly higher (though for SSDs, much improved over HDDs) access latency, and are non-volatile, used for long-term storage of programs and data, and as the backing store for virtual memory paging/swapping."},{"type":"paragraph","content":"**Memory hierarchy principle:** these technologies are organized into a hierarchy — registers, then cache (SRAM), then main memory (DRAM), then secondary storage (SSD/disk) — with speed and cost per bit decreasing, and capacity increasing, as one moves down the hierarchy, exploiting the principle of locality of reference so that the small amount of fast, expensive memory near the top effectively services the vast majority of memory accesses, while the much larger, cheaper, slower memory near the bottom provides the necessary total capacity, achieving a system that approaches the speed of the fastest technology at close to the cost per bit of the slowest."},{"type":"paragraph","content":"**Quantitative comparison of access times and costs:** to make this hierarchy concrete, typical relative access latencies (illustrative, not exact for any specific chip) might be: CPU registers, under 1 nanosecond; SRAM cache (L1), roughly 1-4 nanoseconds; SRAM cache (L2/L3), roughly 10-40 nanoseconds; DRAM main memory, roughly 50-100 nanoseconds; SSD (flash-based) secondary storage, roughly 20,000-100,000 nanoseconds (tens of microseconds); and magnetic hard disk, roughly 5,000,000-10,000,000 nanoseconds (several milliseconds) due to mechanical seek and rotational delay. This roughly 5-6 order-of-magnitude spread in latency across the hierarchy is precisely why the memory hierarchy design — keeping the small working set of currently relevant data in the fastest levels — has such a dramatic impact on overall system performance; a program whose memory accesses are poorly localized (causing frequent cache misses and page faults down to disk) can run orders of magnitude slower than one with good locality, even on identical hardware."},{"type":"paragraph","content":"**Emerging and specialized memory technologies:** beyond the conventional hierarchy, several specialized technologies address particular needs — NVRAM (Non-Volatile RAM) and newer technologies like MRAM (Magnetoresistive RAM) and phase-change memory aim to combine DRAM-like speed with the non-volatility of flash, potentially reshaping future memory hierarchies by blurring the traditional volatile/non-volatile boundary; and video/graphics memory (VRAM, GDDR variants) is specifically optimized for the high-bandwidth, highly parallel access patterns required by graphics processing, often using wider data buses and different latency-versus-bandwidth trade-offs than conventional system DRAM. Understanding the full spectrum of memory technologies — from the fastest, most expensive registers down through the largest, cheapest secondary storage — is essential for computer architects to make informed trade-offs when designing systems for specific performance, cost, and power budgets."},{"type":"paragraph","content":"**Volatility and power implications:** the volatile technologies (registers, SRAM, DRAM) all lose their stored contents the instant power is removed, meaning any system relying solely on these technologies must have some non-volatile backing store to preserve data across power cycles — this is precisely the role played by ROM/flash-based firmware (which must survive power-off to allow the system to boot) and by secondary storage (which must retain user data and installed programs indefinitely without continuous power). Non-volatile technologies, while essential for persistence, generally exhibit slower write speeds and, in the case of flash memory, a limited number of write/erase cycles before cells begin to wear out, which is why memory-hierarchy and file-system designers must additionally account for write-endurance and wear-leveling considerations specifically when using flash-based (SSD/EEPROM) storage, a concern that does not arise for the purely volatile technologies higher in the hierarchy."},{"type":"paragraph","content":"**Summary table of trade-offs:** ranking the technologies from fastest/most-expensive/smallest-capacity to slowest/cheapest/largest-capacity gives the ordering: registers, SRAM cache, DRAM main memory, flash/SSD, magnetic disk — with volatility present only in the first three and non-volatility characterizing the latter two, illustrating that the memory-technology landscape is fundamentally organized around this single unifying speed-cost-capacity-volatility trade-off curve that every computer architecture course and system design decision must ultimately navigate."},{"type":"paragraph","content":"**Conclusion:** no single memory technology can simultaneously deliver the speed of registers, the capacity of magnetic disk, and the cost-effectiveness of both at once, which is why practical computer systems are always built as a coordinated hierarchy combining several of these technologies rather than relying on any one in isolation — an architectural principle that has remained fundamentally stable even as the specific technologies at each level (SRAM, DRAM, flash) have continued to advance in density and speed over successive hardware generations."}]}},{"id":"computer-architecture-2022-5E1391-pC-q3","number":3,"marks":15,"tags":["Part C"],"text":[{"type":"paragraph","content":"Q.3. Write short notes on:"},{"type":"list","items":["(a) DMA controller","(b) Stacks & queues","(c) Arithmetic pipeline"]}],"answer":{"summary":"A DMA controller autonomously manages block data transfers between I/O devices and memory without CPU intervention; stacks (LIFO) and queues (FIFO) are core linear data structures for storage/scheduling; arithmetic pipelining overlaps stages of complex floating-point operations across specialized segments for higher throughput.","explanation":[{"type":"subheading","content":"(a) DMA controller"},{"type":"paragraph","content":"A DMA (Direct Memory Access) controller is a specialized hardware unit that manages the transfer of a block of data directly between an I/O device and main memory, without requiring the CPU to supervise each individual data word transfer. The CPU initializes the DMA controller by providing it with the starting memory address, the I/O device address, the direction of transfer (read/write), and the total word count for the transfer; the DMA controller then independently generates the necessary memory addresses and control signals, incrementing the address and decrementing the word count after each word transferred, using 'cycle stealing' to briefly take control of the system bus from the CPU for each individual word transfer. Once the entire block transfer is complete, the DMA controller raises a single interrupt to notify the CPU, which then handles only the completion of the whole operation rather than every individual word — this dramatically reduces CPU overhead for high-volume data transfers such as disk I/O, making DMA essential for efficient, high-throughput system design."},{"type":"subheading","content":"(b) Stacks & Queues"},{"type":"paragraph","content":"A stack is a Last-In-First-Out (LIFO) linear data structure, where insertion (push) and removal (pop) both occur only at one end, the top of the stack; it is fundamental to implementing subroutine call/return mechanisms (storing return addresses and saved register/local variable contexts in a 'call stack' or 'activation record stack'), evaluating arithmetic expressions (particularly postfix/Reverse Polish Notation expressions, where operands are pushed and operators pop their arguments and push results), and implementing recursive algorithms. A queue is a First-In-First-Out (FIFO) linear data structure, where insertion (enqueue) occurs at one end (the rear) and removal (dequeue) occurs at the other end (the front); queues are used for buffering asynchronous data streams, managing I/O device request order, task/process scheduling in operating systems, and any situation requiring strict order-of-arrival processing, ensuring fairness by servicing the earliest-arrived item first."},{"type":"subheading","content":"(c) Arithmetic pipeline"},{"type":"paragraph","content":"An arithmetic pipeline applies the general pipelining concept specifically to complex arithmetic operations (particularly floating-point addition, multiplication, and division) by decomposing the operation into a sequence of independent sub-tasks (segments), each handled by dedicated hardware, so that multiple independent arithmetic operations can be in different stages of computation simultaneously. For example, a floating-point addition pipeline might be divided into segments for exponent comparison/alignment, mantissa addition, result normalization, and rounding, with each segment implemented as separate hardware connected by pipeline registers. While one pair of operands is being normalized (a later stage), a new, independent pair of operands can simultaneously begin exponent comparison (the first stage), so that once the pipeline is filled, a new arithmetic result can be produced every clock cycle rather than only after the full multi-stage latency of a single operation, substantially increasing the throughput of numerically-intensive applications like scientific computing, computer graphics, and digital signal processing, which perform very large numbers of floating-point operations."},{"type":"paragraph","content":"**Further detail on DMA transfer modes:** DMA controllers typically support several transfer modes offering different trade-offs between transfer speed and CPU availability — burst mode (block transfer mode), where the DMA controller takes control of the bus and transfers an entire block of data in one continuous sequence without releasing the bus, achieving maximum transfer speed but completely locking out the CPU from bus access for the transfer's duration; and cycle-stealing mode, where the DMA controller transfers only one word at a time, releasing the bus back to the CPU between each word transfer, which is slower overall for the DMA transfer but allows the CPU to continue executing instructions (accessing memory in the gaps between DMA transfers), striking a more balanced compromise for systems where the CPU cannot tolerate being completely blocked for an extended period."},{"type":"paragraph","content":"**Further detail on stack/queue implementations:** in hardware and low-level software, a stack is commonly implemented using a dedicated Stack Pointer (SP) register that always points to the current top of the stack in memory; a PUSH operation decrements (or increments, depending on convention) the SP and writes the new value at that location, while a POP operation reads the value at the current SP location and then adjusts the SP back. A queue can be implemented using two pointers — a front pointer and a rear pointer — into either a linear array (requiring shifting or a circular/ring-buffer wraparound scheme to avoid wasting space as elements are dequeued from the front) or a linked-list structure (allowing dynamic growth without a fixed size limit but with the overhead of pointer-based node allocation). Circular queues, in particular, are widely used in real-time and embedded systems for implementing I/O buffers, since they provide constant-time enqueue/dequeue operations within a fixed, pre-allocated memory region."},{"type":"paragraph","content":"**Further detail on arithmetic pipeline hazards:** like instruction pipelines, arithmetic pipelines can experience hazards when a later operation depends on the result of an earlier operation still in the pipeline (a data dependency), requiring either a pipeline stall (bubble insertion, wasting cycles) or forwarding hardware that routes a partially-computed intermediate result directly to where it is needed rather than waiting for it to complete the full pipeline and be written back to a register. Additionally, since floating-point operations can take a variable number of cycles to complete depending on operand values (e.g., division may require iterative refinement), some arithmetic pipelines are designed as non-linear pipelines with feedback paths, allowing an operation to revisit an earlier segment multiple times before completing, which requires more sophisticated pipeline control logic (a reservation table) to correctly schedule when new operations can safely enter the pipeline without colliding with an operation still cycling through a feedback loop."},{"type":"paragraph","content":"Together, these three topics — DMA controllers, stack/queue data structures, and arithmetic pipelining — represent distinct but complementary techniques for improving overall system throughput: DMA offloads bulk data movement from the CPU, stacks and queues provide the essential organizational primitives for managing control flow and buffered data, and arithmetic pipelining accelerates the numerically-intensive computational core itself, collectively illustrating how modern computer architecture achieves high performance through specialized hardware and data-structure support at every level of the system, from I/O subsystems through to the arithmetic-logic core."}]}}],"examYear":2022}],"loading":false,"error":null}}}

Q1Computer Architecture

Question

Answer