Q3Microcontroller and Embedded Systems

A square wave of frequency 2 kHz has a period of 1/2000 = 500 microseconds, and since a square wave completes one full toggle (high-to-low or low-to-high) transition every half-period, the pin P1.5 must be toggled once every 500/2 = 250 microseconds to produce the required 2 kHz output frequency.

With an 11.0592 MHz crystal, one machine cycle takes 12/11.0592e6 = 1.0851 microseconds as established for another question in this examination, so a 250 microsecond delay requires approximately 250/1.0851 = 230 machine cycles, a delay duration readily achieved using Timer 0 in Mode 1 (16-bit timer), loaded with an initial count value such that exactly 230 machine cycle increments cause it to overflow, or equivalently, and more simply for a hand-written assembly program, using a calibrated software delay loop.

        MOV     TMOD, #01H      ; Timer 0, Mode 1 (16-bit timer)
AGAIN:  CPL     P1.5            ; toggle pin P1.5
        MOV     TH0, #0FFH      ; load timer for approx 250 microsecond delay
        MOV     TL0, #06H       ; (65536 - 230 = 65306 = FF06H)
        SETB    TR0             ; start Timer 0
HERE:   JNB     TF0, HERE       ; wait until Timer 0 overflow flag is set
        CLR     TR0             ; stop Timer 0
        CLR     TF0             ; clear the overflow flag for next round
        SJMP    AGAIN           ; repeat, toggling P1.5 again

In this program, Timer 0 is configured in Mode 1 (a full 16-bit up-counter) and reloaded with the value FF06H before each timing interval, corresponding to 65536 minus 230, so that exactly 230 machine cycle increments are needed to overflow the timer from FF06H back to 0000H, matching the required approximately 250 microsecond half-period delay; the CPL (complement) instruction toggles pin P1.5 on each pass through the AGAIN loop, and since the loop toggles the pin once per 250 microsecond timed interval, the pin output alternates between high and low at exactly this 250 microsecond rate, producing the desired 2 kHz square wave (one full period, consisting of one high half-cycle and one low half-cycle, every 500 microseconds) at pin P1.5.

Number of Interrupts and Default Priority

The basic 8051 microcontroller provides five interrupt sources in total: external interrupt 0 (INT0), Timer 0 overflow interrupt, external interrupt 1 (INT1), Timer 1 overflow interrupt, and the serial port interrupt (shared between the transmit-complete flag TI and the receive-complete flag RI). Enhanced 8051-family devices such as the 8052 add a sixth interrupt source, the Timer 2 overflow/capture interrupt, but the basic 8051 as covered in this unit provides exactly these five sources. The default (power-up, unless reprogrammed through the IP register) priority order among interrupt sources of the same priority level, from highest to lowest, is: external interrupt 0 (highest default priority), Timer 0 overflow interrupt, external interrupt 1, Timer 1 overflow interrupt, and the serial port interrupt (lowest default priority); this fixed default polling sequence determines which interrupt source is serviced first whenever two or more interrupt requests at the same configured priority level (high or low, as set in the IP register) become pending simultaneously.

IE Register Bit Functions

As discussed in relation to another question in this examination, the Interrupt Enable (IE) register bits are: EA (bit 7), the global master interrupt enable, which must be set to 1 to permit any interrupt to be recognized regardless of the state of any individual enable bit; ET2 (bit 5), the Timer 2 interrupt enable, applicable only on enhanced devices with a Timer 2; ES (bit 4), the serial port interrupt enable, controlling whether the TI or RI flags can generate a CPU interrupt; ET1 (bit 3), the Timer 1 overflow interrupt enable; EX1 (bit 2), the external interrupt 1 (INT1) enable; ET0 (bit 1), the Timer 0 overflow interrupt enable; and EX0 (bit 0), the external interrupt 0 (INT0) enable. To actually enable any given interrupt source for use, both the EA master enable bit and the corresponding individual source enable bit must be set to 1 simultaneously, since either bit being cleared is sufficient to block that interrupt source from generating a recognized CPU interrupt.

It is further worth emphasizing that the computed 131.072 millisecond maximum single-overflow delay in Mode 1 assumes the timer counts internal machine cycles (the C/T-bar bit of TMOD cleared to select timer, rather than counter, operation); if the same 16-bit Mode 1 configuration were instead used as an event counter (C/T-bar set), counting external pulses on the T0 or T1 pin rather than internal machine cycles, the same 65536-count range would instead represent the maximum number of external events that can be counted before overflow, with the resulting elapsed real time depending entirely on the external event rate rather than on the fixed 2 microsecond machine-cycle-derived increment period calculated above, illustrating that the practical meaning of the timer's maximum count range differs substantially between its timer and counter modes of operation.

It is further worth noting that the square wave generation program above uses a busy-wait polling loop (JNB TF0, HERE) to detect the timer overflow rather than an interrupt-driven approach, which is a simpler technique appropriate for this dedicated, single-purpose program, but a real embedded application that must simultaneously perform other processing while generating the background square wave would instead typically enable the Timer 0 overflow interrupt (setting ET0 and EA in the IE register, as discussed above) and toggle the P1.5 pin from within the Timer 0 interrupt service routine itself, freeing the main program loop to perform other useful work between successive timer overflow events rather than being forced to wait, blocked, in the polling loop shown above.

It is worth noting finally that this combination of a hand-calculated timer reload value, an assembly program using that value, the enumeration of the five interrupt sources with their default priority order, and the full bit-by-bit description of the IE register together cover every element requested by this multi-part examination question in complete detail.

These four elements together fully answer this question in the depth required by the examination.

Taken together, the square-wave generation program, the enumeration of interrupt sources and their default priority, and the bit-by-bit IE register description above illustrate how a single practical application (generating a precisely timed periodic output signal) draws simultaneously on timer configuration, interrupt or polling-based timing detection, and register-level configuration knowledge, reflecting the genuinely integrated nature of 8051 embedded programming rather than treating timers, interrupts, and register configuration as entirely separate, unconnected topics.

This finalizes the complete answer required for this examination question in full detail as originally set out in the paper text.

All parts of the question, the program, the interrupt count and priority, and the register bit functions, have now been addressed comprehensively.