Q3Microcontroller and Embedded Systems

The 8051 provides five interrupt sources (in the basic 8051 variant): two external hardware interrupts (INT0 on pin P3.2 and INT1 on pin P3.3), two timer overflow interrupts (from Timer 0 and Timer 1), and one serial port interrupt (triggered by either the TI transmit-complete flag or the RI receive-complete flag). Each interrupt source has an associated enable bit in the IE register (discussed in relation to another question in this examination) that must be set, along with the master interrupt enable bit EA, before that source can actually generate a CPU interrupt. Each interrupt source also has an associated priority level, individually configurable as either high or low priority through the corresponding bit in the Interrupt Priority (IP) register; a low-priority interrupt currently being serviced can itself be interrupted by a higher-priority interrupt request, but a high-priority interrupt in progress cannot be interrupted by any other interrupt request regardless of that other request's priority, and if two interrupt requests of the same priority level become pending simultaneously, a fixed, hardware-defined polling sequence determines which is serviced first (the default priority order, from highest to lowest, being external interrupt 0, Timer 0 interrupt, external interrupt 1, Timer 1 interrupt, and finally the serial port interrupt). When an enabled interrupt request is recognized (checked once at the end of every machine cycle by the 8051's internal interrupt-polling hardware), the CPU completes the instruction currently in progress, then automatically pushes the current program counter value onto the stack (but does not automatically save the accumulator, PSW, or other working registers, as discussed for another question in this examination), and finally loads the program counter with the fixed, dedicated interrupt vector address associated with that specific interrupt source (for example, address 0003H for external interrupt 0, or 000BH for the Timer 0 interrupt), causing program execution to jump directly to the corresponding interrupt service routine. Because these interrupt vector addresses are spaced only 8 bytes apart in program memory, the actual interrupt service routine code is often placed elsewhere in program memory, with only a short unconditional jump instruction placed at the vector address itself, redirecting execution to the full ISR located at a more spacious memory location. The interrupt service routine concludes with a RETI (return from interrupt) instruction, which pops the previously saved program counter value back off the stack, resuming execution of the interrupted main program (or lower-priority ISR) exactly where it left off, and additionally clears the internal hardware flag that had blocked further interrupts of the same or lower priority during the just-completed ISR's execution.

Largest Possible Timer Delay in Mode 1 at 6 MHz

Timer Mode 1 configures the timer as a full 16-bit up-counter, capable of counting from 0000H up to FFFFH (a total of 65536, or 2^16, discrete count values) before overflowing back to 0000H and setting the corresponding timer overflow flag. With a 6 MHz crystal, and given the standard 8051 machine cycle duration of 12 oscillator periods, the timer increments once every 12/6e6 = 2 microseconds.

Since Mode 1 provides the full 16-bit counting range of 65536 possible counts before overflow, the largest possible time delay achievable using a single timer overflow in Mode 1 is the full count range multiplied by the increment period: maximum delay = 65536 * 2 microseconds = 131072 microseconds, which equals 131.072 milliseconds.

This result represents the absolute maximum single-overflow delay achievable in Mode 1 at this crystal frequency, corresponding to loading the timer with an initial count of 0000H (rather than any larger starting value, which would reduce the number of counts needed to reach overflow and hence shorten the resulting delay); any time delay requirement longer than this 131.072 millisecond maximum would require either software counting of multiple timer overflow events in sequence, or the use of a lower-frequency crystal, since the fundamental 16-bit counting range and the 12-clock-per-cycle machine cycle structure together set this absolute upper limit on the delay obtainable from any single timer overflow event in Mode 1 at a given crystal frequency.

Interrupt Intervals and Interrupt Density

Interrupt interval refers to the time period between successive occurrences of a given periodic interrupt source, such as the regular, evenly spaced timer overflow interrupts generated when a timer is used in an auto-reload mode to produce a fixed periodic tick; the interrupt interval is a critical design parameter in real-time embedded systems, since it directly determines the maximum permissible execution time of the corresponding ISR (the ISR, together with any other higher- or equal-priority processing that might delay it, must reliably complete well within one interrupt interval, or subsequent interrupt occurrences risk being missed, delayed, or causing an overrun condition in which the system falls progressively further behind real time). Interrupt density refers to the overall frequency or cumulative rate at which interrupts (potentially from multiple different sources) occur and demand CPU attention within a given system, reflecting the total fraction of available CPU processing time and bandwidth that is consumed servicing the combined stream of interrupts from all active sources, rather than the design of any single interrupt source's interval taken in isolation. A system with high interrupt density, in which the CPU is very frequently diverted away from its main background processing task to service interrupts (whether because individual interrupt intervals are very short, because many independent interrupt sources are simultaneously active, or both), leaves correspondingly less net CPU time and bandwidth available for the system's actual background application processing, and can, in the extreme case of sufficiently high interrupt density, result in the CPU spending such a large fraction of its time in interrupt service routines that the intended background task cannot make adequate forward progress at all, a failure mode commonly termed interrupt livelock; both interrupt interval and interrupt density are therefore essential design considerations when architecting the interrupt structure of any real-time embedded system, requiring careful selection of ISR execution time budgets, interrupt priorities, and, where necessary, techniques such as interrupt coalescing or polling-based alternatives to keep overall interrupt density within levels the system's CPU bandwidth can sustainably support.

It is further worth noting that the fixed default interrupt priority order in the 8051 (external interrupt 0 highest, serial port interrupt lowest, as discussed for another question in this examination) applies only when two pending interrupt requests share the same programmed priority level in the IP register; if a designer requires a different relative ordering among a specific pair of interrupt sources, this is achieved not by altering the fixed default polling sequence itself, which is a hardware-determined characteristic of the 8051 core, but by assigning the two sources to different priority levels (high and low) in the IP register, ensuring the more time-critical source is always serviced first regardless of the underlying default polling order that would otherwise apply only among sources sharing the same priority level.