Q2Microcontroller and Embedded Systems

The 8051 instruction set supports five distinct addressing modes, each specifying a different way in which an instruction's operand data is located.

• Immediate addressing: the operand value itself is directly encoded within the instruction as a literal constant, indicated in 8051 assembly syntax by a preceding pound (#) sign; for example, MOV A,#25H loads the literal hexadecimal value 25H directly into the accumulator, with the constant value 25H itself forming part of the instruction's machine code.
• Register addressing: the operand is held in one of the eight general-purpose working registers (R0 through R7) of the currently active register bank; for example, MOV A,R0 copies the contents of register R0 into the accumulator, with the specific register R0 through R7 encoded directly within the instruction's opcode itself.
• Direct addressing: the operand's memory address (an 8-bit address, covering the internal RAM and special function register address space) is explicitly specified within the instruction; for example, MOV A,30H copies the byte stored at internal RAM address 30H into the accumulator, and MOV A,PSW would access the accumulator using the symbolic name for the PSW special function register's direct address.
• Register indirect addressing: the operand's memory address is held in one of the registers R0 or R1 (or, for external data memory access, in the 16-bit DPTR register), with the instruction referencing the register that holds the address rather than a fixed address itself, indicated by an @ symbol preceding the register name; for example, MOV A,@R0 copies the byte located at the internal RAM address currently held in R0 into the accumulator, allowing the actual target address to be computed and varied at run time, which is essential for implementing arrays, lookup tables accessed by a variable index, and similar data structures.
• Indexed addressing: the operand's address is computed as the sum of a base register (either the program counter or the DPTR register) and the accumulator's current contents used as an offset, used specifically for accessing lookup tables stored in program memory; for example, MOVC A,@A+DPTR reads a byte from program memory at the address formed by adding the accumulator's value to DPTR, and copies that byte into the accumulator, commonly used to implement lookup-table-based code conversion routines such as a seven-segment display encoding table.

Inter-Processor Serial Communication via TXD and RXD

The 8051's on-chip UART (Universal Asynchronous Receiver/Transmitter) provides the serial communication capability used for inter-processor communication, with the TXD pin (P3.1) used to transmit outgoing serial data and the RXD pin (P3.0) used to receive incoming serial data, both configured and controlled through the Serial Control (SCON) register and the serial data buffer (SBUF register). To transmit a byte of data, the programmer writes the byte to be sent directly into the SBUF register; this write operation automatically triggers the UART hardware to begin serially shifting the byte out through the TXD pin, framed according to the selected serial mode (most commonly Mode 1, an 8-bit UART mode using one start bit, eight data bits, and one stop bit, at a baud rate set by Timer 1 operating in its auto-reload mode), and upon completion of the transmission, the UART hardware automatically sets the TI (transmit interrupt) flag bit in the SCON register, which the transmitting program (or an associated interrupt service routine, if serial interrupts are enabled) checks or waits upon before writing the next byte to be transmitted, and which must be cleared by software before the next transmission can proceed. To receive a byte of data, the receiving 8051 continuously monitors the RXD pin for an incoming start bit; once a start bit is detected and the incoming byte has been fully shifted in by the UART hardware, the received byte is automatically transferred into the SBUF register (a physically separate receive buffer register, despite sharing the same symbolic SBUF name and address as the transmit buffer) and the RI (receive interrupt) flag bit in SCON is automatically set, signaling the receiving program (or its associated interrupt service routine) that a new byte is available to be read out of SBUF, with the RI flag again requiring explicit software clearing before the next incoming byte can be correctly detected and flagged. For two 8051 devices to communicate with each other over their TXD and RXD lines, the TXD pin of one device is connected to the RXD pin of the other, and vice versa (a standard cross-connected, full-duplex serial link), with both devices configured to the same serial mode, the same baud rate (commonly achieved by configuring both devices' Timer 1 to the same auto-reload value derived from their respective crystal frequencies), and, in multiprocessor communication configurations using Mode 2 or Mode 3, the same additional 9th-bit (multiprocessor communication) protocol convention used to distinguish address bytes from data bytes when multiple receiving devices share a common serial bus.

It is further worth noting that the choice between register indirect addressing (using R0 or R1) and indexed addressing (using the accumulator plus DPTR or the program counter) for accessing data in a table or array is often driven by whether the data resides in internal RAM (favoring register indirect addressing through R0 or R1) or in program memory (favoring indexed addressing through MOVC, since program memory cannot generally be read using the ordinary MOV instruction used for internal RAM access), illustrating that selecting the appropriate addressing mode in practice depends not merely on the desired access pattern but also on which memory space the actual target operand resides within.

This complete treatment of addressing modes and inter-processor serial communication fully satisfies the requirements of this examination question as originally set out in the paper.

This complete answer fully addresses both parts of the question as originally set out in the examination paper.

Both addressing-mode enumeration and the serial communication protocol description above together fully answer this question in the depth required.

Taken together, the five addressing modes and the inter-processor UART communication mechanism described above represent two of the most fundamental building blocks of 8051 assembly programming practice, one governing how any single instruction locates its operand data, and the other governing how two separate microcontroller-based systems exchange that data across a physical link, and a firm grasp of both is a prerequisite for writing any non-trivial 8051 application program.