Q1Microcontroller and Embedded Systems

A CPU is classified as a microcontroller, rather than a general-purpose microprocessor, when it integrates onto a single chip not just the central processing unit but also the complete set of peripheral resources needed for a self-contained embedded control application, without requiring external support chips for basic operation.

• On-chip program memory (ROM, EPROM, or Flash) sufficient to hold the application firmware, eliminating the need for an external program memory chip as is required in a microprocessor-based system.
• On-chip data memory (RAM) for variables, the stack, and general working storage, again eliminating the need for external RAM in most simple embedded applications.
• A number of bidirectional parallel input/output ports, allowing direct connection to external switches, LEDs, sensors, and other simple digital peripherals without additional interfacing logic chips.
• One or more on-chip timer/counter units, used for generating precise time delays, measuring external event durations, or generating periodic interrupts, without requiring an external timer chip.
• A serial communication interface (such as UART) built into the chip, enabling direct serial communication with other devices without external serial interface hardware.
• An interrupt control system supporting multiple internal and external interrupt sources with programmable priority, allowing the CPU to respond promptly to asynchronous events without continuously polling every peripheral.
• A relatively limited, application-specific instruction set and register architecture optimized for control-oriented, bit-level and byte-level operations (such as direct bit-set, bit-clear, and bit-test instructions) rather than for the high-throughput, general-purpose numerical computation emphasized in microprocessor instruction sets.

In short, a microcontroller is best understood as a complete, self-sufficient single-chip computer system optimized for dedicated, embedded control applications, whereas a microprocessor is simply the CPU itself, requiring external memory, I/O, and support chips assembled around it to form a complete functional system.

Program Status Word (PSW)

The Program Status Word is an 8-bit special function register in the 8051 that holds key status flags reflecting the outcome of the most recently executed arithmetic or logical instruction, along with the register bank selection bits used for indirect addressing of the general-purpose register banks. The PSW bits, from bit 7 (most significant) to bit 0 (least significant), are: CY (carry flag, bit 7), set when an arithmetic operation produces a carry-out of the most significant bit, or used as an accumulator for bit-level Boolean operations; AC (auxiliary carry flag, bit 6), set when there is a carry from bit 3 to bit 4 during an addition, used specifically to support BCD (binary-coded decimal) arithmetic correction; F0 (bit 5), a general-purpose flag available for the programmer's own use, with no dedicated hardware function; RS1 and RS0 (register bank select bits, bits 4 and 3), which together select which of the four available register banks (Bank 0 through Bank 3, each containing registers R0 through R7) is currently active for register-addressed instructions; OV (overflow flag, bit 2), set when a signed arithmetic operation produces a result that exceeds the representable range for a signed byte; a reserved bit (bit 1), not used in the 8051; and P (parity flag, bit 0), automatically set or cleared by hardware after every instruction cycle to reflect the parity (even or odd number of 1 bits) of the accumulator's contents, useful for simple error-checking in serial data transmission.

Interrupt Enable (IE) Register

The Interrupt Enable register is an 8-bit special function register that controls which of the 8051's interrupt sources are enabled to generate an actual CPU interrupt, providing both a global interrupt enable/disable control and individual enable/disable control for each specific interrupt source. The bits of the IE register are: EA (bit 7, global interrupt enable), which must be set to 1 to allow any interrupt at all to be recognized by the CPU, acting as a master enable that overrides all individual interrupt enable bits when cleared; ET2 (bit 5, Timer 2 interrupt enable, present only on 8052-family devices with a third timer); ES (bit 4, serial port interrupt enable), enabling interrupts generated by the serial port's transmit or receive completion flags; ET1 (bit 3, Timer 1 overflow interrupt enable); EX1 (bit 2, external interrupt 1 enable); ET0 (bit 1, Timer 0 overflow interrupt enable); and EX0 (bit 0, external interrupt 0 enable). To enable any specific interrupt source, the programmer must set both the global enable bit EA and the corresponding individual enable bit for that source; for example, enabling Timer 0 interrupts requires setting both EA and ET0.

RAM Structure of the 8051

The 8051 microcontroller provides 128 bytes of on-chip internal RAM (in the basic 8051 variant, with an additional 128 bytes of extended internal RAM present in enhanced variants such as the 8052), organized into three functionally distinct regions.

• Register banks (addresses 00H to 1FH): this 32-byte region is organized as four separate banks of eight general-purpose registers each, labeled R0 through R7 in every bank; only one bank is active at any given time, selected by the RS1 and RS0 bits of the PSW register discussed above, allowing fast context switching between different sets of working registers, for example when entering an interrupt service routine, without needing to explicitly save and restore the working registers to the stack.
• Bit-addressable RAM (addresses 20H to 2FH): this 16-byte (128-bit) region can be accessed either as ordinary bytes using standard byte-oriented instructions, or as individual addressable bits using the 8051's dedicated bit-oriented instructions (such as SETB, CLR, and various bit-test instructions), providing an efficient means of maintaining and manipulating individual software flags and single-bit control variables without needing to perform byte-wide read-modify-write operations.
• General-purpose (scratchpad) RAM (addresses 30H to 7FH): this remaining 80-byte region is available for general use as variable storage, the program stack, or any other data storage need of the application program, accessed only through standard byte-oriented direct or indirect addressing.

Beyond this internal RAM, the 8051's special function registers (SFRs), including the PSW and IE registers discussed above, the accumulator, the B register, the stack pointer, the data pointer, the I/O port latches, and the timer and serial port control and data registers, occupy a separate address range from 80H to FFH, addressed using the same direct addressing mode as the general-purpose RAM but representing entirely distinct physical registers rather than ordinary memory locations; only a subset of the addresses in this upper 80H-FFH range actually correspond to implemented SFRs, with unimplemented addresses in this range simply unavailable for use, unlike the fully populated 00H-7FH internal RAM region described above.