Q5IC Technology

The standard bipolar integrated circuit fabrication sequence for a discrete npn transistor structure begins with a p-type substrate, into which a heavily doped n-type buried layer is first implanted and diffused in a selectively masked region, forming a low-resistance path that will later underlie the transistor's collector region and substantially reduce collector series resistance; a lightly doped n-type epitaxial layer (as discussed for another question in this examination, subject to the autodoping considerations also discussed there) is then grown over the entire wafer, incorporating the buried layer beneath it. A p-type isolation diffusion is then performed, penetrating from the epitaxial surface down to the p-type substrate, surrounding each individual transistor region with a p-n junction that, when reverse-biased in circuit operation, electrically isolates neighboring devices from one another (junction isolation). Within each isolated epitaxial island, a p-type base diffusion is performed to form the transistor's base region, followed by a heavily doped n-type emitter diffusion within the base region to form the emitter, and a heavily doped n-type collector contact diffusion elsewhere within the same epitaxial island (contacting down to the low-resistance buried layer) to provide a low-resistance collector terminal. Contact windows are then opened through a passivating oxide layer down to the emitter, base, and collector contact regions, and a metallization layer is deposited and patterned to form the final interconnect wiring.

LOCOS Method

LOCOS (Local Oxidation of Silicon) is a device isolation technique, historically the dominant isolation method before shallow trench isolation displaced it in more advanced technology nodes, in which a thin stress-relief pad oxide and an overlying silicon nitride masking layer are patterned so that the nitride covers and protects the intended active device areas while leaving the intended field (isolation) regions exposed; the wafer is then subjected to a long, high-temperature wet oxidation step, during which a thick field oxide grows selectively only in the exposed (unmasked) isolation regions, since the nitride layer is highly resistant to oxidant diffusion and effectively blocks oxide growth beneath the protected active areas. A well-known limitation of LOCOS is the formation of a lateral, tapered oxide encroachment at the edge of the masked active area, commonly called the bird's beak (due to its characteristic tapered cross-sectional shape resembling a bird's beak), caused by lateral oxidant diffusion beneath the edge of the nitride mask, which consumes some of the intended active device area and limits how closely adjacent devices can be packed, a limitation that ultimately motivated the industry's transition to shallow trench isolation for the tighter device spacing required in advanced CMOS technology.

SOI Techniques

Silicon-on-insulator (SOI) technology fabricates active transistor devices in a thin layer of single-crystal silicon that sits directly atop a buried insulating oxide layer, rather than atop bulk silicon substrate material as in conventional processing, electrically isolating each device from the underlying substrate and from neighboring devices far more completely than bulk isolation techniques such as junction isolation or trench isolation can achieve. Common techniques for forming SOI wafers include SIMOX (separation by implantation of oxygen), in which a high dose of oxygen ions is implanted deep beneath the silicon surface and a subsequent high-temperature anneal causes the implanted oxygen to react with the surrounding silicon and coalesce into a continuous buried silicon dioxide layer, leaving a thin single-crystal silicon layer above it; and wafer bonding with layer transfer (such as the Smart Cut process), in which a thermally oxidized donor wafer is implanted with hydrogen to create a weakened cleavage plane at a controlled depth, then bonded face-down to a second handle wafer, after which a thermal or mechanical process splits the donor wafer along the hydrogen-implanted cleavage plane, transferring only a thin single-crystal silicon layer (atop the buried oxide that had been grown on the donor wafer before bonding) onto the handle wafer. SOI technology offers several benefits over bulk silicon processing, including elimination of the parasitic latch-up problem (discussed for another question in this examination) since devices are no longer connected to a shared bulk substrate through which the parasitic bipolar feedback loop operates, reduced parasitic junction capacitance (since the source and drain junctions terminate directly on the buried insulating oxide rather than extending into a conductive substrate), and consequently improved circuit speed and reduced power consumption, making SOI technology particularly attractive for high-performance and low-power microprocessor and RF circuit applications despite the higher cost of SOI starting material compared to conventional bulk silicon wafers.

It is also worth further emphasizing that both the LOCOS and SOI techniques discussed here address the same underlying goal, device isolation, but at fundamentally different structural levels: LOCOS (and its successor, shallow trench isolation) isolates individual devices laterally from one another on a conventional bulk substrate through a physical oxide barrier between adjacent active areas, while SOI isolates devices vertically from the substrate itself by placing the entire active silicon layer atop a buried insulator, and modern advanced CMOS technology frequently combines both approaches simultaneously, using shallow trench isolation for lateral device-to-device isolation together with an SOI substrate for vertical device-to-substrate isolation, achieving the benefits of both isolation strategies in a single, unified process technology for the most demanding high-performance and low-power circuit applications.

It is also worth noting that the bipolar fabrication sequence described here, while conceptually simpler than the multi-well, multi-implant CMOS process discussed for another question in this examination, nonetheless requires equally careful control of diffusion depths and doping profiles at each step, since the base width (the vertical distance between the emitter-base and base-collector junctions) directly determines the transistor's current gain and frequency response, making precise control of the base diffusion depth and profile just as critical to bipolar device performance as precise control of channel length and threshold voltage is to CMOS device performance in the twin-tub process described elsewhere in this examination.

In summary, the bipolar IC fabrication sequence together with the LOCOS and SOI technical notes addresses both the specific bipolar process flow requested and the two additional isolation-related short notes required by this examination question.

This complete treatment of the bipolar fabrication sequence together with the LOCOS and SOI technical notes fully satisfies the requirements of this examination question as originally set out in the paper.