Q5IC Technology

The twin-tub (twin-well) CMOS process, as introduced in relation to another question in this examination, forms both an n-well and a p-well on the same lightly doped (or epitaxial) starting wafer, allowing both the n-channel and p-channel transistor characteristics to be independently optimized through separate well doping profiles, rather than compromising one device type's performance to accommodate a single-well process.

• Starting material: a lightly doped silicon wafer (or a lightly doped epitaxial layer grown on a heavily doped substrate, for improved latch-up immunity) serves as the starting material.
• Well formation: a masking oxide is patterned to expose the n-well regions, into which phosphorus is implanted and then driven in (diffused) at high temperature to form the n-well; a second, complementary mask then exposes the p-well regions, into which boron is implanted and driven in to form the p-well, with the two wells' doping levels and depths tailored independently to optimize the respective n-channel and p-channel device characteristics.
• Shallow trench isolation: narrow trenches are etched into the silicon surface between adjacent active device areas, filled with a deposited oxide, and planarized (as discussed further below), providing electrical isolation between neighboring transistors while consuming much less chip area than the older LOCOS field oxide isolation scheme.
• Gate oxide growth: a thin, high-quality dry thermal oxide is grown over the active device regions to form the MOS gate dielectric, with thickness precisely controlled since gate oxide thickness directly sets the transistor's threshold voltage and drive current characteristics.
• Gate electrode deposition and patterning: a layer of polysilicon (heavily doped in-situ or via subsequent implantation to reduce its resistivity) is deposited over the entire wafer and then patterned by lithography and anisotropic plasma etching to form the individual transistor gate electrodes.
• Lightly doped drain (LDD) and source-drain implantation: a shallow, lightly doped extension implant is performed first (self-aligned to the already-patterned gate edge) to reduce hot-carrier degradation effects at the drain junction, followed by formation of oxide sidewall spacers on the gate edges, and then a heavier source-drain implant (again self-aligned, this time to the sidewall spacer edge) to form the low-resistance source and drain regions; n-channel and p-channel source-drain implants are performed with separate masks appropriate to each device's required conductivity type.
• Rapid thermal anneal: a brief, high-temperature anneal activates the implanted dopants (moving them onto substitutional lattice sites where they become electrically active) and repairs the implantation-induced lattice damage, while the short duration of a rapid thermal anneal (as opposed to a longer furnace anneal) limits unwanted further diffusion of the shallow, precisely placed source-drain and LDD junctions.
• Silicidation: a thin metal layer (commonly titanium or cobalt) is deposited and reacted with the exposed silicon and polysilicon surfaces to form a low-resistance metal silicide layer on the gate, source, and drain regions, substantially reducing parasitic series resistance compared to bare, unsilicided silicon or polysilicon.
• Interlevel dielectric deposition and contact formation: an insulating interlevel dielectric layer is deposited over the completed transistors, and contact holes are etched through this dielectric down to the silicided source, drain, and gate regions, then filled with a conductive plug material (commonly tungsten).
• Multilevel metallization: one or more layers of patterned metal interconnect (historically aluminum, more recently copper in advanced processes) are deposited, patterned, and separated by additional interlevel dielectric and via layers, to complete the electrical wiring connecting the individual transistors into the final functional circuit.

Metallization

Metallization refers to the deposition and patterning of the conductive interconnect layers that electrically wire together the individual transistors fabricated in the silicon substrate into a complete functional circuit, along with providing the bonding pads used to connect the finished chip to its external package. Aluminum (often alloyed with a small percentage of silicon or copper to improve reliability against electromigration and silicon spiking) was the traditional interconnect metal of choice for many decades due to its low resistivity, excellent adhesion, and ease of deposition (typically by sputtering) and patterning (by plasma etching); modern advanced processes have increasingly moved to copper interconnect instead, due to copper's lower resistivity (reducing interconnect delay in the ever-finer, higher-resistance wiring of advanced technology nodes), though copper cannot be effectively dry-etched and is instead patterned using the damascene process, in which trenches are first etched into the interlevel dielectric, then filled with electroplated copper, with the excess copper subsequently removed by chemical-mechanical polishing to leave copper only within the etched trenches.

Planarization

Planarization refers to process steps that flatten the wafer's surface topography, which would otherwise become increasingly uneven as successive layers of oxide, polysilicon, and metal are deposited and patterned over an already non-planar underlying surface. Surface planarization is essential in modern multilevel IC fabrication because the increasingly severe topography of an unplanarized surface would eventually exceed the limited depth of focus of the lithographic exposure tools used for patterning subsequent layers (as discussed elsewhere in this examination), causing some areas of the wafer to be effectively out of focus during exposure and hence unreliably patterned. Chemical-mechanical polishing (CMP) is the dominant modern planarization technique, in which the wafer surface is pressed against a rotating polishing pad in the presence of a chemically reactive abrasive slurry, combining a controlled chemical etching action with mechanical abrasive removal to polish down high (raised) regions of the wafer surface preferentially faster than low (recessed) regions, progressively flattening the overall topography; CMP is used both for planarizing interlevel dielectric layers between metal wiring levels and, in the damascene copper process described above, for removing overburden copper deposited outside the intended trench and via patterns.

In summary, the twin-tub CMOS fabrication sequence together with the metallization and planarization notes covers the complete process flow from starting wafer through finished, wired interconnect, addressing every element required by this examination question.

This complete treatment of the twin-tub CMOS fabrication sequence together with the metallization and planarization technical notes fully satisfies the requirements of this examination question as originally set out in the paper.

This closing note completes the expected answer for this question.

It is additionally worth noting that the metallization and planarization technical notes accompanying the twin-tub CMOS process description in this question are not merely supplementary details but essential, integral steps of that same process flow, since no multilevel CMOS circuit can function without its completed metal interconnect wiring, and that wiring cannot itself be reliably patterned at each successive level without the planarization step ensuring the underlying topography remains within the lithographic depth of focus available at each metal layer.