Q1IC Technology

Point defects arise fundamentally from thermodynamic equilibrium: at any temperature above absolute zero, the crystal's free energy is minimized not by a perfectly defect-free lattice but by an equilibrium concentration of vacancies and self-interstitials, since the entropy increase associated with a small population of such defects outweighs the energy cost of creating them, with the equilibrium defect concentration increasing exponentially with temperature; point defects can also be introduced non-equilibrium by ion implantation damage, by rapid quenching from a high growth or anneal temperature that traps a higher-than-equilibrium defect concentration, or by the incorporation of impurity atoms occupying substitutional or interstitial lattice sites. Surface defects (stacking faults and grain boundaries) arise primarily from disruptions to the stacking sequence of atomic planes during crystal growth, often nucleated by a pre-existing point defect cluster, a piece of particulate contamination on the growing crystal or wafer surface, or mechanical stress during growth or subsequent thermal processing; grain boundaries specifically arise when two crystal regions of different orientation grow together and meet, as occurs in polycrystalline material or at a poorly controlled seed-crystal interface. Volume defects (precipitates and voids) arise from the aggregation of point defects or impurity atoms into three-dimensional clusters once their concentration locally exceeds the solid solubility limit at the given temperature, such as oxygen precipitates that nucleate and grow during high-low-high temperature anneal sequences, or vacancy-cluster voids that can form during the crystal growth process itself if the growth conditions favor a supersaturation of vacancies at certain points along the crystal.

Changes During Fabrication Processing

As a wafer proceeds through the many high-temperature process steps of device fabrication (oxidation, diffusion, annealing), the defect population is not static but continually evolves: point defects generated or injected during one process step (for example, self-interstitials injected during oxidation, known as oxidation-enhanced diffusion, or vacancies and interstitials generated by ion implantation damage) diffuse through the crystal and can either recombine and annihilate each other, be captured at existing extended defects (dislocations, stacking faults, or precipitates), or aggregate to nucleate entirely new extended defects if their local supersaturation becomes large enough. Repeated thermal cycling can grow existing oxygen precipitates larger (Ostwald ripening, in which larger precipitates grow at the expense of smaller ones to minimize total interfacial energy), can dissolve small, unstable precipitate nuclei that formed during a lower-temperature step if a subsequent step is at higher temperature, or can generate secondary defects such as dislocation loops punched out around a growing precipitate as it exceeds the elastic strain limit of the surrounding lattice; this evolving defect population is precisely why gettering (discussed in detail for another question in this examination) is engineered into the process flow to control where these evolving defects preferentially form, ensuring that they end up away from active device regions rather than degrading device electrical characteristics.

EGS from MGS

Metallurgical grade silicon (MGS), typically about 98-99 percent pure, is produced by the carbothermic reduction of quartzite (silicon dioxide) with carbon in a submerged-arc furnace, following the overall reaction SiO2 + 2C to Si + 2CO, but this purity level (with metallic and other impurities at the percent level) is entirely inadequate for semiconductor device fabrication, which requires purity levels of parts per billion or better. Electronic grade silicon (EGS) is obtained from MGS through a purification sequence exploiting the volatility and selective distillation of a silicon-hydrogen-chlorine compound.

• Step 1, hydrochlorination: powdered MGS is reacted with anhydrous hydrogen chloride gas in a fluidized bed reactor at around 300 degrees Celsius, producing trichlorosilane (SiHCl3) along with other chlorosilane byproducts and hydrogen gas, via the reaction Si + 3HCl to SiHCl3 + H2.
• Step 2, purification by fractional distillation: trichlorosilane has a low boiling point (about 32 degrees Celsius) that is well-separated from the boiling points of the metal chloride impurities also formed during hydrochlorination, allowing repeated fractional distillation to remove essentially all metallic impurity chlorides and yield highly purified trichlorosilane.
• Step 3, chemical vapor deposition (Siemens process): the purified trichlorosilane vapor, mixed with hydrogen gas, is passed over resistively heated, thin silicon filament rods (seed rods) inside a bell-jar reactor at around 1100 degrees Celsius, where the reverse reaction SiHCl3 + H2 to Si + 3HCl deposits ultra-pure polycrystalline silicon onto the growing rods, gradually building up large-diameter polysilicon rods of electronic grade purity as deposition continues over many hours.

The block diagram for EGS production can be represented as a linear process flow: Quartzite and Carbon, feeding into the Arc Furnace (carbothermic reduction) producing Metallurgical Grade Silicon (MGS), feeding into the Hydrochlorination Reactor (with HCl gas input) producing crude Trichlorosilane (SiHCl3) plus byproducts, feeding into the Fractional Distillation Column producing Purified Trichlorosilane, feeding into the Siemens CVD Reactor (with H2 gas input and heated seed rods) producing Electronic Grade Silicon (EGS) polysilicon rods as the final output, which are subsequently used as the source charge material for Czochralski or float-zone single-crystal growth.

It is also worth noting that the segregation-coefficient-driven variation in dopant concentration along the length of a grown crystal ingot, of the same type analyzed in the accompanying numerical for this question, is a practical concern in commercial crystal growth, since a segregation coefficient different from unity (as for essentially all common silicon dopants) means that a single grown ingot cannot supply wafers of perfectly uniform resistivity along its entire length purely from a single, unstirred or uncompensated melt; commercial crystal pullers address this by carefully controlling pull rate and melt replenishment (in continuous or semi-continuous Czochralski growth) or by selecting the useable length of a given ingot to stay within an acceptable resistivity variation band for the intended device application, directly informed by the same normal-freezing segregation relationship used in the numerical calculation above.

It is further worth noting that both point, surface, and volume defects and the electronic-grade-silicon purification sequence discussed in this question are connected through a shared underlying theme of purity and structural perfection: the multi-stage EGS purification process (hydrochlorination, fractional distillation, and Siemens CVD deposition) is specifically engineered to reduce metallic and other impurity concentrations to the parts-per-billion level required before crystal growth even begins, since these same impurities, if not adequately removed at the EGS stage, would otherwise nucleate and aggravate the very volume defects (precipitates) and enhance the diffusion-related generation of point and surface defects discussed above during the subsequent high-temperature device fabrication sequence, meaning upstream material purity and downstream crystallographic defect control are two tightly linked aspects of the same overall goal of producing high-quality, high-yield semiconductor devices.