Q1IC Technology

After a single-crystal silicon ingot has been grown by either the Czochralski (Cz) method (pulling a rotating seed crystal slowly from a rotating crucible of molten silicon) or the float-zone method (passing a molten zone along a polycrystalline rod suspended without any crucible contact, using RF induction heating), the resulting cylindrical ingot must undergo a sequence of mechanical shaping steps before it can be used for wafer fabrication.

• Crystal trimming (end removal): the seed and tail ends of the grown ingot, which have non-uniform diameter and crystal quality due to the initial neck-down and final termination of the growth process, are cut off and discarded, leaving the useful constant-diameter body of the ingot.
• Diameter grinding (shaping): although the ingot grows with an approximately circular cross-section, the diameter typically varies somewhat along the ingot's length and is not perfectly uniform or perfectly circular; the ingot is therefore mounted in a centerless grinding machine and ground down to a precise, uniform target diameter within tight tolerance, appropriate for standard wafer size specifications (such as 150mm, 200mm, or 300mm).
• Orientation flat or notch grinding: a flat (in older, smaller-diameter wafers) or a small V-shaped notch (in modern larger-diameter wafers) is ground along the length of the ingot at a precisely controlled crystallographic orientation, serving to identify the wafer's crystal orientation and (in the case of flats on older wafers) also the conductivity type and dopant, for use in subsequent automated wafer handling and alignment during device fabrication.
• Wafer slicing: the shaped, ground ingot is sliced into individual thin wafers using a diamond-impregnated inner-diameter saw blade or, in modern high-throughput processes, a wire saw using a slurry of abrasive particles, with wafer thickness and slicing precision controlled to minimize kerf loss (wasted material converted to sawdust) and to maintain flatness and parallelism between the two wafer faces.
• Wafer lapping: the sawn wafers, which have a rough, damaged surface from the slicing process, are lapped (using a rotating lapping plate with an abrasive slurry) on both sides to remove saw damage and achieve a flat, parallel surface finish with a tightly controlled overall wafer thickness.
• Edge rounding (edge contouring): the sharp outer edge of each wafer, which is highly susceptible to chipping and cracking during subsequent handling, is mechanically rounded off using a shaped grinding wheel, substantially improving the mechanical robustness of the wafer against edge-originated fractures.
• Etching: a chemical etch (typically a mixture of nitric, hydrofluoric, and acetic acids) is used to remove the microscopic subsurface crystal damage remaining from the lapping and edge-rounding mechanical operations, since this damage would otherwise act as a source of crystallographic defects and mechanical weakness during subsequent high-temperature processing.
• Polishing: the wafer surface intended for device fabrication (the front, or 'device' side) is chemically-mechanically polished to an extremely smooth, mirror-like, and flat finish, essential for achieving the tight depth-of-focus and pattern fidelity requirements of modern photolithography.
• Cleaning and inspection: the finished wafers undergo a final rigorous cleaning sequence (such as the RCA clean described elsewhere in this examination) and are inspected for particulate contamination, flatness, and crystallographic defects before being packaged and shipped for device fabrication.

Boron Concentration Calculation via Normal Freezing (Segregation)

During crystal growth from a melt, dopant impurities distribute unevenly between the solid (growing crystal) and the remaining liquid melt, characterized by the segregation coefficient k, defined as the ratio of solid to liquid dopant concentration at the solid-liquid interface at any instant, k = Cs/Cl. Under the normal freezing (Scheil equation) approximation, which assumes complete mixing in the liquid melt but no diffusion back into the already-solidified crystal, the solid concentration as a function of the fraction of the melt solidified, fs, is given by Cs(fs) = kC0(1-fs)^(k-1), where C0 is the initial (original) melt concentration before any solidification has occurred.

Rather than needing to separately determine the unknown initial melt concentration C0, the ratio of solid concentration at two different fraction-solidified points can be taken directly, since C0 and k cancel out appropriately: Cs(fs2)/Cs(fs1) = [(1-fs2)/(1-fs1)]^(k-1). Substituting the given values fs1 = 0.05 with Cs1 = 2x10^8 atoms/cm^3, fs2 = 0.4, and k = 0.8:

Computing the ratio inside the parentheses: 0.6/0.95 = 0.6316. Raising this to the power (k-1) = -0.2 gives (0.6316)^(-0.2) = 1.0963 approximately, since raising a number less than one to a small negative power yields a value slightly greater than one.

Therefore, Cs(0.4) = Cs(0.05) 1.0963 = 2x10^8 1.0963 = 2.19x10^8 atoms/cm^3 approximately. This result shows that, because the segregation coefficient of 0.8 is less than unity (meaning boron is rejected into the liquid phase somewhat as the crystal solidifies, since less boron partitions into the solid than remains in the liquid at equilibrium), the boron concentration in the solid crystal gradually rises as solidification proceeds and the melt becomes progressively enriched in the rejected dopant, consistent with the calculated increase in solid concentration from the earlier fraction solidified (0.05) to the later fraction solidified (0.4).

It is worth further emphasizing that each of these shaping steps must be performed with tight dimensional and surface-quality tolerances, since defects or non-uniformities introduced at this early stage of wafer preparation (before any device fabrication has even begun) propagate through the entire subsequent process flow and can limit the ultimate yield of functioning devices; for instance, insufficient edge rounding leaves the wafer vulnerable to chipping during the many wafer-handling steps of a modern fab, residual subsurface damage from incomplete etching after lapping can nucleate dislocations during later high-temperature processing, and inadequate final polishing can compromise the depth of focus available during critical lithography steps performed much later in the process flow, illustrating why crystal shaping, though performed before any active device processing, is nonetheless a critical determinant of final device yield and reliability.

It is further worth noting that the choice between the Czochralski and float-zone growth methods themselves (before any of the shaping steps described above are even applied) is driven by the specific purity and application requirements of the intended device: Czochralski growth, using a quartz crucible to hold the molten silicon charge, inevitably introduces a small but significant oxygen concentration into the grown crystal from the dissolving crucible wall, which is beneficial for standard CMOS and memory applications since the resulting oxygen supports the intrinsic gettering process discussed for another question in this examination, whereas float-zone growth, being entirely crucible-free, produces extremely low oxygen and carbon content silicon required for high-power, high-voltage devices and detector-grade silicon where oxygen-related defects would otherwise degrade breakdown voltage and carrier lifetime, illustrating that the crystal shaping steps described above apply broadly to ingots from either growth method, while the choice of growth method itself is determined by the target device application's purity requirements.