RTUEE / EC / EEEYr 2019 · Sem 72019

Q1Wireless Communication

Question

16 marks

1. (a) What is PN sequence? Discuss about the property of PN sequence and also draw a Block diagram to generate 15 length M sequence using flip flop. [8]

(b) Explain Transmitter and Receiver of DSSS with suitable diagram. [8]

Answer

PN Sequence, Properties, 15-Length M-Sequence Generator, and DSSS Transmitter/Receiver

A Pseudo-Noise (PN) sequence is a deterministically generated binary sequence that exhibits statistical properties closely resembling those of a truly random (white noise) binary sequence, while being exactly reproducible at both the transmitter and receiver since it is generated by a known, deterministic algorithm (most commonly a linear feedback shift register, LFSR) rather than a genuinely random physical process. PN sequences are the foundation of spread-spectrum communication, used to spread the transmitted signal's bandwidth (DSSS) or to control pseudo-random frequency hopping (FHSS).

  • Balance property: within each period of the sequence, the number of 1s and 0s differs by at most one, giving near-equal representation of both binary values.
  • Run-length property: among the runs (consecutive strings of identical bits), approximately half of all runs have length 1, a quarter have length 2, an eighth have length 3, and so on in geometric progression, mimicking the run-length statistics of genuinely random binary noise.
  • Correlation property: the periodic autocorrelation function is sharply peaked (equal to the full sequence energy) at zero shift and drops to a small, nearly constant value (ideally -1/N for a maximal-length sequence of period N) at every nonzero shift, enabling reliable code synchronization/acquisition by searching for this correlation peak.
4-Stage LFSR Generating 15-Length M-SequenceD1D2D3D4X

A 15-length (2^4 - 1) m-sequence is generated using a 4-stage shift register (D1 through D4) with feedback taken from two specific stages (chosen according to a primitive polynomial over GF(2), such as x^4 + x + 1), XORed together and fed back to the input of the first stage D1. On each clock pulse, the register contents shift by one stage (D4 receives the value previously in D3, and so on), while the new value entering D1 is the XOR of the two tap outputs. Starting from any nonzero initial register state, this feedback arrangement cycles through all 15 possible nonzero 4-bit states exactly once before repeating, producing a maximal-length sequence of period 2^4 - 1 = 15 bits, with the near-ideal autocorrelation and balance properties described above (in a 15-bit m-sequence, there are exactly 8 ones and 7 zeros, satisfying the balance property to within the minimum possible one-bit difference).

DSSS Transmitter and Receiver

The DSSS transmitter takes the narrowband data signal, modulates it (commonly via BPSK), and then multiplies (XORs, in the binary domain, or multiplies as plus/minus-1 values in the analog domain) the modulated signal by a high-chip-rate PN sequence, producing a wideband spread signal whose bandwidth is approximately equal to the PN code's chip rate rather than the original data bandwidth. This spread signal is then upconverted to the desired RF carrier frequency and transmitted. The DSSS receiver performs the inverse operation: the received RF signal is downconverted to baseband or IF, and then correlated (multiplied and integrated/lowpass-filtered) against a locally generated, precisely time-synchronized replica of the identical PN sequence used at the transmitter, which exactly despreads the signal back to its original narrowband form (since the PN sequence multiplied by itself equals 1), after which conventional BPSK demodulation recovers the original data bits. Any interference or jamming signal not correlated with the receiver's PN reference is instead spread out (rather than despread) by this correlation operation, so only a small fraction of the interferer's power falls within the narrowband post-despreading filter bandwidth, providing the fundamental interference-rejection processing gain that is the primary motivation for using DSSS.

The choice of a 4-stage register generating exactly a 15-length sequence in this example is not arbitrary: for an LFSR of length m using a primitive feedback polynomial, the maximum possible sequence period achievable is always exactly 2^m - 1 (never 2^m, since the all-zero register state is excluded, as it would otherwise cause the register to remain permanently stuck at all-zeros once reached). This is precisely why m-sequences are also referred to as maximal-length sequences - they achieve the theoretical maximum possible period for a given register length, and it is this maximal period property, combined with the near-ideal autocorrelation and balance properties described above, that makes m-sequences generated from carefully chosen primitive polynomials the preferred building block for PN sequence generation in practical spread-spectrum systems, whether used directly or as the starting point for constructing more elaborate code families such as Gold codes with improved cross-correlation properties suited to multi-user CDMA operation.

The specific choice of which two (or more) shift-register stages to tap for the feedback XOR is determined entirely by the coefficients of the chosen primitive polynomial; not every possible tap combination yields a maximal-length sequence, and identifying the primitive polynomials for a given register length is itself a well-studied problem in the mathematics of finite fields (Galois field GF(2^m) theory), with standard reference tables of primitive polynomials available for register lengths used in practical communication system design, allowing a system designer to directly look up an appropriate tap configuration rather than needing to independently rediscover it through exhaustive search.

Finally, it should be noted that the same PN sequence generation and correlation principles described here for a single, short 15-length illustrative m-sequence scale up directly to the much longer PN sequences (of period 2^m - 1 for register lengths m typically ranging from about 10 to over 40 in real systems) used in practical DSSS and CDMA communication systems, where a longer period provides both a higher achievable processing gain (since processing gain is directly proportional to the ratio of chip rate to data rate, and a longer PN period at a fixed chip rate supports a correspondingly lower minimum data rate before the sequence must repeat) and a greater degree of signal-interception resistance for any party lacking knowledge of the exact PN sequence and its current phase.

This overview of PN sequence properties, m-sequence generation, and the DSSS transmit/receive chain completes the requested explanation.

In a complete DSSS transceiver implementation, the acquisition and tracking of the correct PN code phase at the receiver (before the correlation-based despreading described above can even begin) is itself a nontrivial engineering problem, typically solved using a serial-search or matched-filter acquisition stage to find the approximate correct code phase, followed by a delay-locked loop to maintain fine, continuous phase tracking once initial acquisition succeeds.

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