Q5Digital Signal Processing

(a) Block Diagram Representation for Discrete-Time LTI Systems

Any discrete-time LTI system, described by a linear constant-coefficient difference equation, can be represented graphically as a block diagram built from exactly three basic functional elements:

• Adder: a summing junction with two (or more) signal inputs and a single output equal to the sum of the inputs, represented graphically as a circle with a plus sign or simply as converging arrows into a single output arrow.
• Constant multiplier (scalar gain): multiplies an input signal by a fixed constant coefficient (drawn from the difference equation's coefficients), represented as a triangle or a labeled arrow indicating the multiplication factor.
• Unit delay element: delays a signal by exactly one sample period, represented by a box labeled z^-1 (in z-transform notation) or D (delay), implementing the operation y(n)=x(n-1).

Any difference equation can be represented as an interconnection of these three elements: each y(n-k) term corresponds to a chain of k unit delays applied to the output feedback path, each x(n-k) term corresponds to a chain of k unit delays applied to the input feedforward path, each coefficient corresponds to a constant multiplier applied along the respective signal path, and the final combination of all these weighted, delayed terms is combined using adders to produce y(n).

(b) Direct Form and Cascade Form for H(z) = z^-1 / [(1+(1/3)z^-1)(1-(1/4)z^-1)]

Expanding the denominator: (1+(1/3)z^-1)(1-(1/4)z^-1) = 1 + (1/3-1/4)z^-1 - (1/12)z^-2 = 1 + (1/12)z^-1 - (1/12)z^-2, so:

Direct Form I: realizes the numerator (feedforward) and denominator (feedback) sections using two separate delay chains - the input x(n) passes through its own delay chain (here, just a single z^-1 delay, since the numerator is simply z^-1, i.e., y_ff(n)=x(n-1)) feeding into a summing junction, which also receives feedback contributions from the output's own delayed and scaled values (y(n-1) scaled by -1/12, and y(n-2) scaled by +1/12), corresponding to the poles at z=-1/3 and z=1/4.

Cascade Form

The cascade form factors H(z) into a product of simpler first-order (or second-order) sections connected in series, exploiting the fact that the given transfer function's denominator is already factored into two first-order terms. One natural factoring is:

where H1(z) realizes the pole at z=-1/3 and H2(z) realizes both the single delay (numerator z^-1) and the pole at z=1/4 - each of these two first-order sections is itself realized as a simple one-pole direct-form structure (a single feedback delay/multiply/add loop), and the two sections are connected in series (cascade), with H1's output feeding directly into H2's input, together implementing the complete transfer function H(z) as their product, exactly as required by the cascade/series-connection property of LTI systems (transfer functions of series-cascaded systems multiply together).

Why Direct Form I Motivates Canonic (Direct Form II) Structures

The Direct Form I structure realized above uses two entirely separate delay chains - one for the feedforward (numerator) path and a second, independent one for the feedback (denominator) path. For this particular transfer function, the feedforward path requires 1 delay element (for the single z^-1 term in the numerator) while the feedback path requires 2 delay elements (for the second-order denominator), giving a total of 3 delay elements in the complete Direct Form I realization. In general, for an Mth-order numerator and Nth-order denominator, Direct Form I requires M+N total delay elements - noticeably more memory (storage registers) than is fundamentally necessary, since the theoretical minimum number of delays needed to realize any such transfer function is only max(M,N), not M+N.

This redundancy motivates the canonic Direct Form II structure, which recognizes that the feedforward and feedback computations can share a single intermediate delay chain rather than each maintaining its own separate set of delayed values - an intermediate signal w(n) is computed first to satisfy the denominator (feedback) part of the difference equation, and the same delayed values of w(n) are then reused (rather than re-computed or independently re-delayed) to form the numerator (feedforward) combination that produces the final output. For the transfer function considered in this problem, this reduces the delay-element count from 3 (Direct Form I) down to max(1,2)=2 (Direct Form II/canonic form), a saving that becomes increasingly significant for higher-order filters, where Direct Form I's M+N delay requirement can be roughly double the canonic form's max(M,N) requirement.

Structure Comparison Summary

• Direct Form I: total delays = M+N (here, 1+2=3); separate feedforward and feedback delay chains; simplest to derive directly from the difference equation; more memory required, but each delay chain's internal signal has a straightforward, easily interpreted meaning (delayed input or delayed output).
• Direct Form II (canonic): total delays = max(M,N) (here, max(1,2)=2); a single shared intermediate delay chain; minimum possible memory for a given transfer function; the intermediate signal w(n) does not correspond directly to any physically meaningful system quantity, only to an internal computational variable.
• Cascade form: total delays depend on the specific factoring chosen, but each individual first/second-order section can itself be realized in canonic form, so the overall structure remains close to the theoretical minimum while also gaining modularity (each section can be independently scaled, analyzed, or adjusted).
• Quantization/coefficient-sensitivity considerations: Direct Form I and II, when realizing a single, high-order transfer function directly (rather than as a cascade of low-order sections), tend to be highly sensitive to coefficient quantization error - small rounding errors in the multiplier coefficients can shift the realized poles/zeros substantially, particularly for poles clustered close together or close to the unit circle, sometimes even causing an intended stable filter to become unstable after quantization. Cascade (and parallel) realizations, built from low-order (first- and second-order) sections, are significantly more robust to this coefficient-quantization sensitivity, since each individual section's pole/zero locations are perturbed largely independently and by a smaller relative amount, which is why cascade/parallel structures (rather than a single high-order direct form) are strongly preferred in practical fixed-point digital filter implementations.

It is worth emphasizing why the choice between Direct Form I and Direct Form II (canonic form) matters in a practical DSP implementation beyond the pure delay-element count: in fixed-point hardware or software implementations, the intermediate signal w(n) computed at the canonic-form node (between the feedback and feedforward sections) can, for certain pole locations close to the unit circle, exhibit a much larger dynamic range than either the input or the output signal, creating a risk of internal arithmetic overflow that would not necessarily be apparent from the input-output specification alone - this is one reason why cascade and parallel realizations, built from individually well-conditioned low-order (first- and second-order) sections rather than one large direct-form realization, are generally preferred in practice, since each section's internal dynamic range is easier to bound, scale, and analyze independently, and coefficient quantization error introduced by finite word-length representation of the a_k and b_k coefficients has a more localized, predictable effect on the overall pole-zero locations of the cascaded system.

For this specific transfer function H(z) = z^-1/[(1+(1/3)z^-1)(1-(1/4)z^-1)], the cascade form is particularly attractive because the two first-order sections have well-separated, real poles at z=-1/3 and z=1/4, both safely inside the unit circle (guaranteeing a stable, causal system), and each section can be independently realized with just one delay element and two multiplier coefficients, making the cascade form both economical in hardware resources (multipliers and adders) and numerically robust, since a coefficient quantization error in one section's multiplier only perturbs that section's own pole location slightly rather than potentially destabilizing the entire higher-order system as could occur with a single, larger direct-form realization of the full second-order denominator.