Q5Microwave Engineering 2

(a) Steps of MOSFET Fabrication

• Wafer preparation: starting with a cleaned, polished single-crystal silicon wafer of appropriate background doping type and concentration, forming the substrate on which the MOSFET will be built.
• Field oxidation: a relatively thick layer of silicon dioxide is grown (typically by thermal oxidation) across the entire wafer surface, providing electrical isolation between adjacent devices and serving as a barrier layer for subsequent selective doping steps.
• Photolithographic patterning: a photoresist layer is applied and selectively exposed/developed through a patterned mask to define the specific active-area regions where the actual transistor will be formed, with the field oxide subsequently etched away in these defined active-area windows.
• Well/source-drain region doping: dopant atoms (of the opposite type to the substrate, for the source/drain regions, since these regions must reverse the local conductivity type to form the pn junctions with the substrate/body) are introduced via ion implantation or diffusion, followed by an annealing step to activate the implanted dopants and repair crystal damage.
• Gate oxide growth: a very thin, high-quality silicon dioxide layer is grown specifically in the channel region between the source and drain, forming the critical gate dielectric whose thickness and quality directly determine the transistor's threshold voltage and gate capacitance characteristics.
• Gate electrode formation: a conductive gate electrode material (traditionally heavily-doped polysilicon, or in modern advanced processes, a metal gate stack) is deposited over the gate oxide and patterned to define the precise gate length, which directly determines the transistor's channel length and hence its switching speed and current-carrying capability.
• Metallization and interconnect: contact openings are etched through the overlying oxide to the source, drain, and gate regions, and metal (traditionally aluminum, or copper in advanced processes) is deposited and patterned to form the electrical interconnections between individual transistors and to external circuit connections.
• Passivation and final testing: a final protective passivation layer is deposited over the completed circuit to protect it from contamination and mechanical damage, after which the wafer is electrically tested, diced into individual chips, and packaged.

(b) Principle of Operation of n-Channel JFET

The n-channel Junction Field-Effect Transistor (JFET) consists of a bar of lightly-doped n-type semiconductor material, forming the conducting channel between two ohmic contacts labeled source and drain, with two heavily-doped p-type regions diffused into opposite sides of the n-type channel (and electrically connected together), forming the gate terminal.

Operation: when a small drain-to-source voltage VDS is applied (with the gate at the same potential as the source, VGS=0), current flows through the n-type channel from drain to source (conventional current), with the channel behaving essentially as an ordinary resistive semiconductor bar under this condition. When a reverse-bias voltage is applied between the gate and source (VGS negative, for an n-channel JFET, since the gate is p-type and the channel is n-type, so a negative gate voltage reverse-biases the gate-channel pn junction), a depletion region forms at the gate-channel junction, extending into the n-type channel and thereby reducing the effective width (and hence the conducting cross-sectional area) of the channel available for current flow. As the magnitude of the reverse gate bias is increased further, the depletion regions extending from the two opposing gate regions grow progressively wider, further narrowing the conducting channel, until at a sufficiently large reverse gate voltage (called the pinch-off voltage, VP), the two depletion regions meet at the channel's center, completely 'pinching off' the channel and reducing the drain current to a very small residual value.

Channel narrowing and saturation: since the drain end of the channel is at a higher positive potential (relative to the source, assuming conventional n-channel JFET biasing) than the source end, the gate-to-channel reverse bias is actually greater near the drain end than near the source end (because the effective reverse bias at any point along the channel is the sum of the applied gate-source voltage and the local channel voltage drop at that point) — this causes the depletion region to be wider near the drain and narrower near the source, giving the channel a characteristic wedge/tapered shape. As drain voltage is increased further (for a fixed gate bias), the channel eventually pinches off first at the drain end while remaining open near the source, and beyond this point, further increases in drain voltage produce very little additional increase in drain current (since the channel's conducting profile near the pinch-off point becomes largely independent of further drain voltage increase), giving rise to the characteristic saturation region of the JFET's drain current-voltage output characteristic, in which drain current becomes primarily controlled by gate voltage and only weakly dependent on drain voltage — this voltage-controlled, saturating current characteristic, achieved without requiring any forward gate current (since the gate-channel junction remains reverse-biased throughout normal JFET operation, drawing only a very small reverse leakage current), is the essential operating principle that makes the JFET useful as a high-input-impedance amplifying and switching device.

Comparison of MOSFET and JFET fabrication and structural philosophy: it is instructive to contrast the MOSFET fabrication sequence described above with the JFET structure discussed in part (b), since both are voltage-controlled field-effect devices but achieve gate control through fundamentally different mechanisms. The MOSFET's gate is electrically isolated from the channel by a deposited (or thermally grown) insulating oxide layer, giving it an extremely high (effectively infinite, at DC) gate input resistance regardless of gate bias polarity, whereas the JFET's gate forms a direct pn junction with the channel, meaning the gate must always be kept reverse-biased (for the n-channel JFET, gate voltage must remain negative or zero relative to the channel) to maintain its otherwise high input impedance, since forward-biasing the gate-channel junction would cause significant gate current to flow, fundamentally altering the device's intended operating behavior. This distinction in gate structure is why MOSFETs, once fabricated with sufficiently thin and reliable gate oxide, became the dominant device technology for modern digital and analog integrated circuits requiring bidirectional gate voltage swing and minimal gate loading, while JFETs remain useful in specific analog and RF applications valuing their generally lower noise and simpler structure for certain classes of circuit.

Additional detail on channel modulation and the JFET transconductance characteristic: the rate at which drain current changes with gate voltage (the JFET's transconductance, gm) is a key small-signal parameter derived directly from the pinch-off/channel-narrowing physics described above, and is typically expressed through Shockley's square-law equation ID = IDSS(1-VGS/VP)^2, where IDSS is the maximum (saturation) drain current at VGS=0 and VP is the pinch-off voltage. This square-law relationship (rather than a purely linear one) reflects the fact that the depletion region's width, and hence the remaining conducting channel cross-section, varies with the square root of the local reverse-bias voltage along the channel, giving the JFET a distinctly non-linear transfer characteristic that must be accounted for in both small-signal amplifier bias-point design (choosing an operating point on this curve for a desired gm) and in analyzing the JFET's inherent third-order intermodulation distortion behavior in RF amplifier applications.