Q2Microprocessor
Question
Q.2. Draw T-states & Machine cycles of STAX & CMP.
Answer
STAX (an 8085 register-indirect memory-write instruction) takes 2 machine cycles (Opcode Fetch + Memory Write, 7 T-states total), while CMP (a register-to-accumulator comparison instruction) takes just 1 machine cycle (Opcode Fetch only, 4 T-states), since CMP operates entirely on internal registers with no external memory access beyond the opcode fetch itself.
STAX (Store Accumulator Indirect), e.g., STAX B or STAX D: this 1-byte instruction stores the accumulator's content into the memory location addressed by the BC or DE register pair (register-indirect addressing). Its execution comprises 2 machine cycles: M1 — Opcode Fetch (4 T-states: T1-T4, during which the opcode is fetched from the memory location pointed to by the Program Counter, decoded, and the PC is incremented); M2 — Memory Write (3 T-states: T1-T3, during which the address held in the BC/DE register pair is placed on the address bus, and the accumulator's content is written to that memory location via the data bus with the WR control signal asserted). Total: 2 machine cycles, 7 T-states.
CMP (Compare), e.g., CMP r: this 1-byte instruction compares the accumulator's content with the content of the specified register r, by internally performing a subtraction (A - r) and setting the flags (Zero, Carry, Sign, Parity, Auxiliary Carry) according to the result, without actually modifying the accumulator's stored value. Since both operands (the accumulator and register r) are already located within the CPU's internal register set, no external memory access is required beyond fetching the instruction's own opcode — its execution comprises just 1 machine cycle: M1 — Opcode Fetch (4 T-states: T1-T4), during which the opcode is fetched, decoded, and the entire compare operation is performed internally within the same machine cycle. Total: 1 machine cycle, 4 T-states.
This comparison illustrates the general 8085 timing principle: instructions requiring an external memory access (beyond the initial opcode fetch, which every instruction requires) need additional machine cycles for each such access, while instructions operating purely on internal CPU registers complete in the minimum single machine cycle, making register-only operations significantly faster to execute than those involving memory read/write, a key consideration in optimizing time-critical assembly language routines.