Q6Microprocessor
Question
Q.6. Draw the timing diagram of STA.
Answer
The STA (Store Accumulator Direct) timing diagram shows an opcode fetch machine cycle followed by two memory-read cycles (to fetch the 16-bit address) and one memory-write cycle (to store the accumulator content at that address), spanning a total of 4 machine cycles / 13 T-states.
The STA addr instruction (3 bytes: opcode + low address byte + high address byte) stores the accumulator's contents into the specified 16-bit memory address, and its timing diagram comprises 4 machine cycles: M1 (Opcode Fetch, 4 T-states — fetching the STA opcode from memory), M2 (Memory Read, 3 T-states — fetching the low-order byte of the address), M3 (Memory Read, 3 T-states — fetching the high-order byte of the address), and M4 (Memory Write, 3 T-states — writing the accumulator's content to the now-assembled 16-bit memory address), giving a total instruction execution time of 4+3+3+3 = 13 T-states. Each machine cycle's timing diagram shows the ALE (Address Latch Enable) pulse at the start (T1), the address on the multiplexed AD0-AD7/A8-A15 bus, and the RD or WR control signal asserted during the appropriate T-states to indicate a memory read or write operation respectively.