Q4Microprocessor

The 8255 Programmable Peripheral Interface (PPI) is a versatile, general-purpose parallel I/O expansion chip commonly used with 8085/8086-family microprocessors to add additional programmable parallel input/output ports, housed in a 40-pin DIP package.

Pin Diagram Overview

Key pins include: PA0-PA7 (Port A, 8 bidirectional I/O lines), PB0-PB7 (Port B, 8 bidirectional I/O lines), PC0-PC7 (Port C, 8 bidirectional I/O lines, which can also be split into two independent 4-bit halves, PC-upper and PC-lower, for handshaking control signals in Modes 1 and 2); D0-D7 (the bidirectional data bus connecting to the microprocessor's data bus, used to transfer control words and I/O data); RD and WR (Read and Write control input signals from the microprocessor); CS (Chip Select, enabling this specific 8255 chip when the microprocessor addresses it); A0, A1 (address lines selecting which internal register — Port A, B, C, or the Control Word Register — is being accessed for a given read/write operation); RESET (resetting the 8255 to its default configuration); and Vcc, GND (power supply pins).

Operational Modes

Mode 0 (Basic/Simple I/O): each of Ports A, B, and the two 4-bit halves of Port C can be independently configured as either a simple input or a simple output port, with no handshaking signals — data is transferred whenever the microprocessor directly performs a read or write to the relevant port, suitable for simple, unconditional (non-handshaken) parallel I/O such as directly reading switch inputs or driving LED/relay outputs.

Mode 1 (Strobed I/O with Handshaking): Ports A and/or B are configured as input or output ports operating with handshaking, using specific bits of Port C automatically reassigned as dedicated handshake control signals (such as STB — Strobe input, signaling that new input data is available; IBF — Input Buffer Full, an output signal acknowledging receipt of data; OBF — Output Buffer Full; and ACK — Acknowledge, an input confirming the receiving device has taken the output data), enabling reliable data transfer with an external peripheral device that itself generates or requires these handshaking signals, such as a printer or a data-acquisition instrument requiring transfer synchronization.

Mode 2 (Bidirectional Strobed I/O): available only for Port A, this mode configures Port A as a single bidirectional 8-bit bus, capable of both sending and receiving handshaken data over the same physical 8 pins (using additional Port C bits for the combined set of input and output handshaking signals needed for both directions), suited to applications requiring two-way handshaken communication with an external device over a shared bidirectional parallel bus, such as certain complex peripheral or inter-processor communication interfaces.

The specific operating mode for each port (or port-half) is selected by writing an appropriate Control Word to the 8255's internal Control Word Register (accessed by placing the combination A1=1, A0=1 on the address lines during a write operation), where individual bits of this control word designate the desired mode for Port A, the direction (input/output) for each port in Mode 0, and select Mode 0, 1, or 2 operation as required by the specific application.

Control Word format (Mode 0/1/2 selection): the Control Word Register's most significant bit (D7) acts as a mode-set flag — when D7=1, the remaining bits of the byte written are interpreted as the Mode Set control word (selecting operating modes and I/O directions for the three ports); when D7=0, the byte is instead interpreted as a Bit Set/Reset control word, allowing any individual bit of Port C alone to be directly set or cleared without needing to read-modify-write the entire port, a convenient feature for driving individual status/handshake output lines on Port C. Within the Mode Set control word, bit D6 selects Group A's mode (0 for Mode 0, 1 for Mode 1, and Mode 2 is selected by a different specific bit combination involving D6-D5), bit D5 (combined with D6) further distinguishes Mode 1 from Mode 2 for Group A, bit D4 sets Port A's direction (1=input, 0=output), bit D3 sets Port C-upper's direction, bit D2 selects Group B's mode (0 for Mode 0, 1 for Mode 1 — Group B does not support Mode 2), bit D1 sets Port B's direction, and bit D0 sets Port C-lower's direction — since Port C is split into two independently-directioned 4-bit halves in Mode 0, unlike Ports A and B which are each controlled as a single 8-bit unit.

Group A and Group B concept: the 8255 internally treats its three ports as belonging to two functional groups — Group A, comprising Port A and the upper 4 bits of Port C, and Group B, comprising Port B and the lower 4 bits of Port C — with each group's operating mode (0, 1, or for Group A only, additionally Mode 2) selected somewhat independently via the control word, meaning, for example, that Port A could be configured in Mode 1 (strobed I/O, using upper Port C bits for handshaking) while Port B is simultaneously configured in Mode 0 (simple I/O), giving considerable flexibility to mix different operating modes across the two port groups within a single 8255 chip according to the specific mixed requirements of a given interfacing application.

Practical application example: a common use of the 8255 is to interface a matrix keypad and a seven-segment or LCD display simultaneously to an 8085/8086 system that itself provides no dedicated parallel I/O of its own — Port A (configured in Mode 0 as input) reads keypad row/column line states, Port B (configured in Mode 0 as output) drives seven-segment display data, and Port C provides additional control lines (such as a keypad column-scan output and a display digit-select output), all through a single 8255 chip addressed at a specific I/O or memory address range determined by the system's address-decoding logic connected to the 8255's CS pin, illustrating the 8255's role as a general-purpose, flexible parallel I/O expansion solution for microprocessor-based systems lacking sufficient built-in I/O capability of their own.

Why a dedicated PPI chip was needed for 8085-based systems: unlike the 8051 microcontroller (which integrates I/O ports directly on-chip, as discussed elsewhere in this paper), the 8085 microprocessor itself provides no dedicated parallel I/O ports at all beyond its address/data bus and a small number of dedicated control/serial lines (SID, SOD) — any parallel I/O capability in an 8085-based system must therefore be added externally via a peripheral interface chip such as the 8255, connected to the system's address, data and control buses exactly like an external memory device, but responding to I/O-mapped or memory-mapped addresses reserved for peripheral access rather than program/data storage. This illustrates a key architectural distinction highlighted elsewhere in this paper between microprocessor-based systems (requiring external memory and I/O support chips to form a complete computer system) and microcontroller-based systems (which integrate this I/O capability on-chip), with the 8255 PPI representing the classic, standard solution historically used to add flexible parallel I/O to 8085/8086-family microprocessor systems.