Q4Microprocessor
Question
Q.4. Draw the T-states and Machine cycles for the following instructions: (a) CMP (b) STAX (c) LDA (d) STA
Answer
CMP r takes 1 machine cycle (4 T-states, opcode fetch only), STAX takes 2 machine cycles (7 T-states, opcode fetch + memory write), LDA addr takes 4 machine cycles (13 T-states, opcode fetch + 2 address-byte reads + 1 data read), and STA addr takes 4 machine cycles (13 T-states, opcode fetch + 2 address-byte reads + 1 data write).
(a) CMP r (Compare register with Accumulator): a 1-byte instruction comparing the accumulator with register r entirely within the CPU's internal registers, requiring no external memory access beyond the instruction's own opcode fetch. Timing: M1 — Opcode Fetch (4 T-states). Total: 1 machine cycle, 4 T-states.
(b) STAX Rp (Store Accumulator Indirect via BC or DE): a 1-byte instruction storing the accumulator's content into the memory location addressed by the specified register pair (BC or DE). Timing: M1 — Opcode Fetch (4 T-states); M2 — Memory Write (3 T-states, writing the accumulator's content to the address held in the register pair). Total: 2 machine cycles, 7 T-states.
(c) LDA addr (Load Accumulator Direct): a 3-byte instruction loading the accumulator with the content of the specified 16-bit memory address. Timing: M1 — Opcode Fetch (4 T-states); M2 — Memory Read (3 T-states, fetching the low-order address byte); M3 — Memory Read (3 T-states, fetching the high-order address byte); M4 — Memory Read (3 T-states, reading the data byte from the now-assembled 16-bit address into the accumulator). Total: 4 machine cycles, 13 T-states.
(d) STA addr (Store Accumulator Direct): a 3-byte instruction storing the accumulator's content into the specified 16-bit memory address. Timing: M1 — Opcode Fetch (4 T-states); M2 — Memory Read (3 T-states, fetching the low-order address byte); M3 — Memory Read (3 T-states, fetching the high-order address byte); M4 — Memory Write (3 T-states, writing the accumulator's content to the now-assembled 16-bit address). Total: 4 machine cycles, 13 T-states.
This comparison shows the general 8085 timing pattern: instructions requiring more bytes (a 3-byte instruction like LDA/STA needs 2 additional memory-read cycles just to fetch its own address operand bytes, beyond the opcode fetch) and more external memory accesses (a data read or write beyond the operand fetch) both add proportionally more machine cycles and T-states to the total execution time, which is why simple, register-only 1-byte instructions like CMP execute fastest, while 3-byte, memory-referencing instructions like LDA and STA take the longest of these four examples.