Q7Microprocessor

The 8051 microcontroller supports the following addressing modes: Immediate addressing, where the operand data value itself is specified directly within the instruction (e.g., MOV A, #30H); Register addressing, where the operand is held in one of the working registers R0-R7 of the currently active register bank (e.g., MOV A, R0); Direct addressing, where the instruction specifies the actual 8-bit address of the internal RAM or SFR location holding the operand (e.g., MOV A, 40H); Register-indirect addressing, where a register (R0 or R1, or DPTR for external memory) holds the address of the memory location containing the actual operand (e.g., MOV A, @R0); Indexed addressing, where the sum of the DPTR (or PC) register and the accumulator's value forms the effective address, used specifically for accessing lookup tables stored in code (program) memory (e.g., MOVC A, @A+DPTR); and Relative addressing, used in conditional jump instructions, where the target address is specified as a signed offset relative to the current program counter value (e.g., SJMP, or the various conditional jump instructions like JZ, JNZ).