{"pinia":{"ui":{"prefs":{"theme":"system","textScale":"md","fontFamily":"sans","reducedMotion":false,"highContrast":false}},"academy":{"universities":[],"universitySummaries":[{"slug":"rtu","name":"RTU","fullName":"Rajasthan Technical University","branches":[{"slug":"first-year-common","name":"First Year (Common)"},{"slug":"computer-science","name":"Computer Science"},{"slug":"mechanical","name":"Mechanical"},{"slug":"civil","name":"Civil"},{"slug":"ai-data-science","name":"AI & Data Science"},{"slug":"ee-ec-eee","name":"EE / EC / EEE"}]},{"slug":"aktu","name":"AKTU","fullName":"Dr. A. P. J. Abdul Kalam Technical University","branches":[{"slug":"first-year-common","name":"First Year (Common)"},{"slug":"computer-science","name":"Computer Science"}]}],"activePapers":[{"id":"ee-ec-eee-digital-electronics-2023","title":"Digital Electronics (2023)","subjectSlug":"digital-electronics","subjectName":"Digital Electronics","universitySlug":"rtu","branchSlug":"ee-ec-eee","year":2,"semester":4,"examYear":2023,"paperCode":"4E1324","questions":[{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-parta-q1","number":1,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"State the associative property of boolean algebra."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-parta-q2","number":2,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"List different digital logic families."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-parta-q3","number":3,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Differentiate between a conventional encoder and a priority encoder."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-parta-q4","number":4,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Draw the truth table for a half adder circuit and write the boolean expressions for sum and carry."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-parta-q5","number":5,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Write excitation table of D flip - flop."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-parta-q6","number":6,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Write about race around condition."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-parta-q7","number":7,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"What are the advantages and disadvantages of R-2R ladder D/A converter."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-parta-q8","number":8,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"State the advantages and applications of sample and hold circuits."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-parta-q9","number":9,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Differentiate between static RAM and dynamic RAM."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-parta-q10","number":10,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"What is a programmable logic array? How it differs from ROM."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partb-q1","number":1,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Perform each of the following conversions :\n\na. $(444.456)_{10}$ in to octal number.\nb. $(A3B)_{16}$ in to decimal number.\nc. $(2D5)_{16}$ in to binary number.\nd. $(115)_{10}$ in to hexadecimal number."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partb-q2","number":2,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Compare the characteristics of TTL and CMOS logic families."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partb-q3","number":3,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Using K-map, minimize the expression\n\n$$F(A,B,C,D) = \\sum m(1,5,7,9,11,13,15).$$"}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partb-q4","number":4,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Explain 4 - bit serial in parallel out register."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partb-q5","number":5,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Draw the logic diagram and timing sequence of a 4 - bit ring counter."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partb-q6","number":6,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Explain the terms accuracy and resolution for D/A converter."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partb-q7","number":7,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Differentiate EPROM and PROM."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partc-q1","number":1,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Define the following with one example :\n\na. Error correcting codes.\nb. Gray code.\nc. Hamming distance.\nd. Even and odd parity code."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partc-q2","number":2,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Using the Quine - McCluskey method, obtain the minimal sum of product expression of the following function.\n\n$$F(A,B,C,D) = \\sum m(0,1,3,7,8,9,11,15).$$"}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partc-q3","number":3,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"a. Convert J-K flip - flop to S-R flip - flop.\nb. Design a 4 - bit synchronous counter."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partc-q4","number":4,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"With a neat block diagram, describe the working of a successive approximation A/D converter and illustrate it with a suitable example."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2023-partc-q5","number":5,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Write a notes on FPGA (field programmable gate array) with a neat diagram."}],"answer":{"summary":"A rigorous theoretical formulation and mathematical definition of the requested electrical concept, strictly adhering to fundamental engineering principles.","explanation":[{"type":"paragraph","content":"This theoretical concept is absolutely foundational to electrical and electronics engineering. It requires the strict application of operational calculus, rigorous boundary conditions, and physical hardware constraints to successfully map complex electromagnetic or signal parameters into their corresponding circuit models, thereby drastically simplifying the calculation of linear and non-linear physical systems."}]}}]},{"id":"ee-ec-eee-digital-electronics-2024","title":"Digital Electronics (2024)","subjectSlug":"digital-electronics","subjectName":"Digital Electronics","universitySlug":"rtu","branchSlug":"ee-ec-eee","year":2,"semester":4,"examYear":2024,"paperCode":"4E1324","questions":[{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-parta-q1","number":1,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Explain digital signals."}],"answer":{"summary":"A digital signal is a discrete-time, discrete-amplitude signal that represents information using two voltage levels corresponding to binary 0 and 1.","explanation":[{"type":"paragraph","heading":"Digital Signals","paragraph":"A digital signal uses a finite set of discrete values to represent information. In binary digital systems, only two voltage levels are used: logic HIGH (1) and logic LOW (0). These are defined by voltage thresholds. For TTL, logic 0 is 0-0.8V and logic 1 is 2.0-5.0V."},{"type":"paragraph","paragraph":"Unlike analog signals that can take any value in a continuous range, digital signals transition abruptly between defined levels. This makes them highly immune to noise and distortion, and ideal for processing, storing, and transmitting information reliably."},{"type":"list","items":["Two voltage levels: HIGH (1) and LOW (0)","Noise immune: small disturbances do not cause errors","Easy to process with Boolean algebra and logic gates","Can be stored and transmitted without degradation"]}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-parta-q2","number":2,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Write the truth table of NAND, operations."}],"answer":{"summary":"The NAND gate outputs 0 only when all inputs are 1; otherwise the output is 1. It is a universal gate.","explanation":[{"type":"paragraph","heading":"NAND Gate Truth Table (2-input)","paragraph":"The NAND (NOT-AND) gate output is the complement of the AND operation."},{"type":"list","items":["A=0, B=0 -> Output=1","A=0, B=1 -> Output=1","A=1, B=0 -> Output=1","A=1, B=1 -> Output=0"]},{"type":"math","math":"Y = \\overline{A \\cdot B}"},{"type":"paragraph","paragraph":"NAND is a universal gate: AND, OR, NOT, NOR, and XNOR gates can all be constructed using NAND gates alone."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-parta-q3","number":3,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Describe TTL."}],"answer":{"summary":"TTL (Transistor-Transistor Logic) is a bipolar digital IC family that uses BJTs for both the input and output stages, operating at 5V with moderate speed and power.","explanation":[{"type":"paragraph","heading":"TTL (Transistor-Transistor Logic)","paragraph":"TTL logic family uses bipolar junction transistors (BJTs). The standard TTL 74xx series operates on a 5V supply. In a basic NAND gate, a multi-emitter transistor drives a phase splitter, whose outputs drive a totem-pole output stage."},{"type":"list","items":["Supply voltage: 5V (+/- 0.25V)","Propagation delay: 10-20 ns (standard TTL)","Power dissipation: ~10 mW per gate","Fan-out: 10 standard TTL loads","Noise margin: 0.4V","Sub-families: Standard TTL (74xx), Low-power (74Lxx), High-speed (74Hxx), Schottky (74Sxx), Advanced Schottky (74ASxx)"]}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-parta-q4","number":4,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Write short note on ALU."}],"answer":{"summary":"An ALU (Arithmetic Logic Unit) is the computational core of a processor that performs arithmetic and logic operations on binary data.","explanation":[{"type":"paragraph","heading":"Arithmetic Logic Unit (ALU)","paragraph":"The ALU is a combinational digital circuit that forms the heart of a microprocessor or CPU. It receives operands from registers and performs selected operations based on control signals (operation select lines)."},{"type":"paragraph","heading":"Operations performed by ALU","paragraph":""},{"type":"list","items":["Arithmetic: addition, subtraction, increment, decrement, multiplication (in advanced ALUs)","Logical: AND, OR, XOR, NOT, NAND, NOR","Shift operations: left shift, right shift, rotate","Comparison: equal, greater than, less than (sets flags)"]},{"type":"paragraph","paragraph":"The ALU outputs the result and sets condition flags (Zero, Carry, Overflow, Sign) that are used for conditional branching in programs."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-parta-q5","number":5,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Explain in brief Flip Flops."}],"answer":{"summary":"Flip-flops are bistable sequential circuits that store one bit of data and change state based on clock and input signals.","explanation":[{"type":"paragraph","heading":"Flip-Flops","paragraph":"A flip-flop is a basic memory element in sequential digital circuits. It has two stable states (0 and 1) and retains its state until a clock edge triggers a change. Types include:"},{"type":"list","items":["SR Flip-Flop: Set-Reset; S=1 sets Q=1, R=1 resets Q=0; S=R=1 is forbidden","D Flip-Flop: Data flip-flop; output Q follows input D at the clock edge; eliminates forbidden state","JK Flip-Flop: J=K=1 causes toggling; most versatile; solves SR ambiguity","T Flip-Flop: Toggle flip-flop; T=1 toggles Q, T=0 holds; used in counters"]},{"type":"paragraph","paragraph":"Flip-flops are used to build registers, counters, memory cells, and finite state machines."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-parta-q6","number":6,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"What do you mean by A/D converters?"}],"answer":{"summary":"An Analog-to-Digital Converter (ADC) converts a continuous analog voltage into a proportional discrete binary number suitable for digital processing.","explanation":[{"type":"paragraph","heading":"A/D Converters","paragraph":"An ADC takes an analog input signal (continuous voltage) and converts it into a digital binary output code. The process involves sampling, quantization, and encoding."},{"type":"list","items":["Sampling: measuring the analog signal at regular intervals (Nyquist rate: fs >= 2 x fmax)","Quantization: rounding the sampled value to the nearest discrete level","Encoding: expressing the quantized level as a binary number"]},{"type":"paragraph","paragraph":"Common ADC types: Flash ADC (fastest), Successive Approximation ADC (most common), Dual-slope ADC (accurate), Sigma-Delta ADC (high resolution). Key parameters are resolution (bits), sampling rate, and accuracy."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-parta-q7","number":7,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Write short note on quantization."}],"answer":{"summary":"Quantization is the process of mapping a continuous range of analog values to a finite set of discrete levels, introducing a quantization error bounded by half the LSB.","explanation":[{"type":"paragraph","heading":"Quantization","paragraph":"In an ADC, the analog input range is divided into 2^n equal intervals for an n-bit converter. Each analog value within an interval is assigned the same digital code. This approximation introduces a quantization error."},{"type":"math","math":"\\text{Quantization step size} = Q = \\frac{V_{FS}}{2^n}"},{"type":"math","math":"\\text{Quantization error} = \\pm \\frac{Q}{2}"},{"type":"paragraph","paragraph":"Increasing the number of bits reduces the step size and hence the quantization error, improving the ADC resolution. The quantization noise limits the signal-to-noise ratio (SNR) of the ADC."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-parta-q8","number":8,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Explain RAM."}],"answer":{"summary":"RAM (Random Access Memory) is a volatile read-write memory in which any storage location can be accessed in the same time regardless of its address.","explanation":[{"type":"paragraph","heading":"RAM (Random Access Memory)","paragraph":"RAM is a type of semiconductor memory that allows data to be read from and written to any location with equal access time. It is volatile: data is lost when power is removed."},{"type":"list","items":["SRAM (Static RAM): uses flip-flop cells; fast, no refresh; used in cache","DRAM (Dynamic RAM): uses capacitor+transistor cells; needs periodic refresh; higher density; used as main memory","Both support random access (any address can be accessed directly)","Typical access time: SRAM 1-10 ns, DRAM 50-100 ns"]},{"type":"paragraph","paragraph":"RAM is used for temporary storage of programs and data currently being processed by the CPU."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-parta-q9","number":9,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Describe CAM."}],"answer":{"summary":"CAM (Content Addressable Memory) is a special memory that is searched by content (data value) rather than by address, returning the address(es) where that content is stored.","explanation":[{"type":"paragraph","heading":"CAM (Content Addressable Memory)","paragraph":"Unlike conventional RAM where you provide an address to get data, CAM works in reverse: you provide data and the CAM searches all locations simultaneously in one clock cycle to find where that data is stored."},{"type":"list","items":["Also called associative memory","Each bit of each word has comparison circuitry","Parallel search across all entries simultaneously - very fast lookup","Ternary CAM (TCAM) has a third state 'don't care' (X) for masked comparisons","Applications: CPU cache tag lookup, TLB (Translation Lookaside Buffer), network routers (IP address lookup), database acceleration"]},{"type":"paragraph","paragraph":"CAM is more expensive and power-hungry than RAM due to the comparison circuitry but provides O(1) lookup time regardless of table size."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-parta-q10","number":10,"marks":2,"tags":["Part A"],"text":[{"type":"paragraph","content":"Write short note on FPGA."}],"answer":{"summary":"FPGA (Field Programmable Gate Array) is a reprogrammable digital IC with configurable logic blocks, programmable interconnects, and I/O blocks used to implement any digital circuit.","explanation":[{"type":"paragraph","heading":"FPGA (Field Programmable Gate Array)","paragraph":"An FPGA is a semiconductor device whose logic function is determined by the user programming it after manufacture, using a hardware description language (VHDL or Verilog). It contains:"},{"type":"list","items":["CLBs (Configurable Logic Blocks): contain LUTs, flip-flops, and carry logic","Programmable Interconnect: configurable routing between CLBs","I/O Blocks: interface to external signals","Modern FPGAs also include embedded multipliers, block RAM, and hard processor cores (ARM/MicroBlaze)"]},{"type":"paragraph","paragraph":"FPGAs can be reprogrammed in the field, allowing design updates after deployment. They are widely used for prototyping, DSP, telecommunications, aerospace, and medical imaging applications."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partb-q1","number":1,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Describe Schottky TTL and CMOS logic."}],"answer":{"summary":"Schottky TTL uses Schottky diodes to prevent transistor saturation for higher speed; CMOS uses complementary MOSFETs for very low power consumption.","explanation":[{"type":"paragraph","heading":"Schottky TTL","paragraph":"Standard TTL gates suffer from slow switching because saturated BJTs take time to come out of saturation (storage time). Schottky TTL solves this by placing a Schottky diode (metal-semiconductor junction with low forward voltage ~0.3V) in parallel with the base-collector junction of each transistor. This clamps the transistor, preventing it from entering saturation."},{"type":"list","items":["Propagation delay: ~3 ns (74S series) vs ~10 ns standard TTL","Higher power: ~20 mW per gate","Advanced Schottky (74AS) and Advanced Low-power Schottky (74ALS) offer better speed-power product"]},{"type":"paragraph","heading":"CMOS Logic","paragraph":"CMOS (Complementary MOS) uses a pair of complementary MOSFETs (pMOS pull-up + nMOS pull-down) for each gate. The complementary structure ensures that only one transistor of each pair conducts in each logic state, giving near-zero static power dissipation."},{"type":"list","items":["Supply voltage: 3V to 15V (standard); 1.8V-3.3V for modern sub-families","Static power: nearly zero (only leakage current)","Dynamic power: proportional to frequency (CV^2 f)","Noise margin: ~30-45% of supply voltage (excellent)","Fan-out: very high (50+ in static CMOS)"]}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partb-q2","number":2,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Obtain decimal equivalent of hexadecimal number $(3A.2F)_{16}$."}],"answer":{"summary":"The hexadecimal number (3A.2F)16 equals 58.171875 in decimal.","explanation":[{"type":"paragraph","heading":"Conversion of (3A.2F)16 to Decimal","paragraph":"Integer part: 3A hex. Fractional part: .2F hex."},{"type":"paragraph","heading":"Integer part: 3A","paragraph":"3 = 3, A = 10"},{"type":"math","math":"3 \\times 16^1 + 10 \\times 16^0 = 48 + 10 = 58"},{"type":"paragraph","heading":"Fractional part: .2F","paragraph":"2 = 2, F = 15"},{"type":"math","math":"2 \\times 16^{-1} + 15 \\times 16^{-2} = \\frac{2}{16} + \\frac{15}{256} = 0.125 + 0.05859375 = 0.18359375"},{"type":"paragraph","heading":"Final Answer","paragraph":""},{"type":"math","math":"(3A.2F)_{16} = 58 + 0.18359375 = 58.18359375_{10}"}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partb-q3","number":3,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Implement the expression using a multiplexer $F( A, B, C, D) = \\sum_m (0, 2, 3, 6, 8, 9, 12, 14)$."}],"answer":{"summary":"F(A,B,C,D) = sum(0,2,3,6,8,9,12,14) can be implemented using a 16:1 MUX by connecting appropriate data inputs to 0, 1, or complement of variables.","explanation":[{"type":"paragraph","heading":"MUX Implementation","paragraph":"Using a 16:1 multiplexer (4 select lines = A,B,C,D), each minterm corresponds to one data input of the MUX. Set the data input to 1 if the minterm is in the ON-set, and 0 otherwise."},{"type":"list","items":["I0 (m0=0000): 1","I1 (m1=0001): 0","I2 (m2=0010): 1","I3 (m3=0011): 1","I4 (m4=0100): 0","I5 (m5=0101): 0","I6 (m6=0110): 1","I7 (m7=0111): 0","I8 (m8=1000): 1","I9 (m9=1001): 1","I10 (m10=1010): 0","I11 (m11=1011): 0","I12 (m12=1100): 1","I13 (m13=1101): 0","I14 (m14=1110): 1","I15 (m15=1111): 0"]},{"type":"paragraph","paragraph":"Select lines S3=A, S2=B, S1=C, S0=D. The MUX selects the appropriate data input based on the ABCD value, directly implementing the truth table. This approach requires no logic minimization."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partb-q4","number":4,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Describe shift registers. Write the application of shift registers."}],"answer":{"summary":"A shift register is a sequential circuit that shifts stored bits one position per clock cycle; types include SISO, SIPO, PISO, and PIPO with applications in serial communication and data conversion.","explanation":[{"type":"paragraph","heading":"Shift Registers","paragraph":"A shift register is a chain of flip-flops where data is shifted from one flip-flop to the next on each clock edge. For an n-bit register, n clock pulses are needed to shift n bits."},{"type":"paragraph","heading":"Types","paragraph":""},{"type":"list","items":["SISO (Serial In Serial Out): data enters and exits serially; used as delay line","SIPO (Serial In Parallel Out): data enters serially, all bits available in parallel; serial-to-parallel converter","PISO (Parallel In Serial Out): data loaded in parallel, shifted out serially; parallel-to-serial converter","PIPO (Parallel In Parallel Out): data loaded and read in parallel; used as buffer register"]},{"type":"paragraph","heading":"Applications","paragraph":""},{"type":"list","items":["Serial communication interfaces (UART, SPI, I2C) - parallel-to-serial and serial-to-parallel conversion","Ring counters and Johnson counters","Digital delay lines (SISO)","CRC generation and checking","Sequence generators","Data storage and temporary buffering"]}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partb-q5","number":5,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Explain sample and hold circuit."}],"answer":{"summary":"A sample and hold circuit samples an analog input at a moment and holds the sampled value constant during the ADC conversion period.","explanation":[{"type":"paragraph","heading":"Sample and Hold Circuit","paragraph":"A sample and hold (S/H) circuit consists of a switch (FET), a holding capacitor (C), and a buffer amplifier. During the sample phase, the switch closes and the capacitor charges to the input voltage. During the hold phase, the switch opens and the capacitor holds the voltage while the ADC performs conversion."},{"type":"svg","svg":""},{"type":"paragraph","heading":"Key Parameters","paragraph":""},{"type":"list","items":["Acquisition time: time for capacitor to charge to the input within specified accuracy","Aperture time: time between hold command and switch fully opening","Hold mode droop: slow discharge of capacitor during hold phase","Feedthrough: signal leakage from input to output during hold mode"]}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partb-q6","number":6,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Write short notes on the following:\n\n(i) Sequential Memory\n(ii) ROM as a PLD"}],"answer":{"summary":"Sequential memory accesses data in a fixed order, unlike random access; ROM can be used as a PLD by programming the AND plane (decoder) outputs into the OR plane.","explanation":[{"type":"paragraph","heading":"(i) Sequential Memory","paragraph":"Sequential memory requires data to be accessed in a specific order, typically first-in-first-out or in the order stored. Unlike RAM (random access), you cannot directly jump to an arbitrary address."},{"type":"list","items":["Examples: magnetic tape, FIFO buffers, shift registers used as delay lines","Access time depends on position of the data relative to current read position","Used in streaming, buffering, pipeline stages"]},{"type":"paragraph","heading":"(ii) ROM as a PLD","paragraph":"A ROM can implement any combinational logic function. An n-input, m-output ROM behaves as a lookup table: the n address lines are the inputs, and each of the m output bits implements one Boolean function of those inputs."},{"type":"list","items":["The AND plane (address decoder) generates all 2^n minterms - this is fixed","The OR plane (data array) is programmable: set each bit to include or exclude a minterm","A ROM with n inputs and m outputs can simultaneously implement m Boolean functions each of up to n variables","Disadvantage: ROM is inefficient for sparse functions since all 2^n minterms are always decoded"]}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partb-q7","number":7,"marks":4,"tags":["Part B"],"text":[{"type":"paragraph","content":"Explain CPLDs."}],"answer":{"summary":"CPLDs (Complex Programmable Logic Devices) are PLDs with multiple PAL-like blocks connected by a programmable interconnect matrix, offering higher capacity than simple PLDs.","explanation":[{"type":"paragraph","heading":"CPLD Architecture","paragraph":"A CPLD contains multiple Logic Blocks (each similar to a PAL/GAL), a Programmable Interconnect Array (PIA) that connects the logic blocks, and I/O blocks. Each logic block has a fixed AND array and programmable OR array with macrocells."},{"type":"svg","svg":""},{"type":"paragraph","heading":"Key Features of CPLDs","paragraph":""},{"type":"list","items":["Non-volatile configuration: EEPROM or Flash-based; retains programming after power off","Predictable timing: fixed interconnect delay (unlike FPGA's variable routing delay)","Instantaneous power-on: no configuration loading time","Capacity: hundreds to thousands of equivalent gates","Used for glue logic, state machines, bus interfaces, and power-on configuration of FPGAs","Examples: Xilinx XC9500, Altera MAX 7000, Lattice ispMACH"]}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partc-q1","number":1,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Design a Gray-to-Binary Code Converter."}],"answer":{"summary":"A Gray-to-Binary converter uses XOR gates where each binary bit is the XOR of all Gray code bits from the MSB down to that position.","explanation":[{"type":"paragraph","heading":"Gray Code to Binary Conversion Rule","paragraph":"For an n-bit Gray code G(n-1)...G1 G0 to binary B(n-1)...B1 B0:"},{"type":"math","math":"B_{n-1} = G_{n-1}"},{"type":"math","math":"B_i = B_{i+1} \\oplus G_i \\quad \\text{for } i = n-2 \\text{ down to } 0"},{"type":"paragraph","heading":"4-bit Example: Gray to Binary","paragraph":"For 4-bit code G3G2G1G0 -> B3B2B1B0:"},{"type":"list","items":["B3 = G3","B2 = B3 XOR G2","B1 = B2 XOR G1","B0 = B1 XOR G0"]},{"type":"paragraph","heading":"Logic Circuit","paragraph":""},{"type":"svg","svg":""},{"type":"paragraph","heading":"Verification Example","paragraph":"Gray code 1011 -> Binary:"},{"type":"list","items":["B3 = G3 = 1","B2 = B3 XOR G2 = 1 XOR 0 = 1","B1 = B2 XOR G1 = 1 XOR 1 = 0","B0 = B1 XOR G0 = 0 XOR 1 = 1","Binary output: 1101 (decimal 13)"]},{"type":"paragraph","heading":"Verification of Gray 1011 = Decimal 13","paragraph":"Gray code: 0000,0001,0011,0010,0110,0111,0101,0100,1100,1101,1111,1110,1010,1011... (13th entry = 1011). Binary 1101 = 13. Correct."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partc-q2","number":2,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Describe BCD Arithmetic and Carry look ahead adder."}],"answer":{"summary":"BCD arithmetic handles carry corrections when a sum exceeds 9; Carry Lookahead Adder (CLA) eliminates the ripple carry delay by computing all carries simultaneously.","explanation":[{"type":"paragraph","heading":"BCD Arithmetic","paragraph":"BCD (Binary Coded Decimal) represents each decimal digit using 4 bits (0000 to 1001). When two BCD digits are added, if the result exceeds 9 (1001) or a carry is generated, a correction of +6 (0110) must be added to bring the result back into valid BCD range."},{"type":"paragraph","heading":"BCD Addition Example","paragraph":"Add BCD 7 (0111) + BCD 6 (0110):"},{"type":"list","items":["Binary sum: 0111 + 0110 = 1101 (decimal 13)","Result 1101 > 1001, so add correction 0110","1101 + 0110 = 10011, which gives BCD carry=1, digit=0011","Result: BCD 13 = carry 1, units digit 3 = 0001 0011"]},{"type":"paragraph","heading":"Carry Lookahead Adder (CLA)","paragraph":"In a ripple carry adder, carry propagates through all stages sequentially, causing delay proportional to n (the number of bits). CLA eliminates this by computing all carries in parallel using generate (G) and propagate (P) signals."},{"type":"math","math":"G_i = A_i \\cdot B_i \\quad \\text{(carry generate)}"},{"type":"math","math":"P_i = A_i \\oplus B_i \\quad \\text{(carry propagate)}"},{"type":"math","math":"C_{i+1} = G_i + P_i \\cdot C_i"},{"type":"paragraph","paragraph":"For a 4-bit CLA, all four carries C1, C2, C3, C4 are computed simultaneously in two gate delays (one for G,P; one for Ci+1), regardless of bit width. This significantly reduces addition time compared to ripple carry."},{"type":"math","math":"C_4 = G_3 + P_3 G_2 + P_3 P_2 G_1 + P_3 P_2 P_1 G_0 + P_3 P_2 P_1 P_0 C_0"}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partc-q3","number":3,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Explain clocked SR flip flop, J-K and D-type flipflops."}],"answer":{"summary":"Clocked SR, JK, and D flip-flops are edge-triggered bistable elements differing in their input behavior: SR has a forbidden state, JK adds toggle capability, D simplifies to a single data input.","explanation":[{"type":"paragraph","heading":"Clocked SR Flip-Flop","paragraph":"The clocked SR flip-flop only responds to inputs when the clock (CLK) is active. S=1 sets Q=1; R=1 resets Q=0; S=R=0 holds state; S=R=1 is forbidden (undefined next state)."},{"type":"list","items":["CLK=0: flip-flop holds state regardless of S, R","CLK=1, S=1, R=0: Q = 1 (Set)","CLK=1, S=0, R=1: Q = 0 (Reset)","CLK=1, S=0, R=0: Q unchanged (Hold)","CLK=1, S=1, R=1: Forbidden"]},{"type":"paragraph","heading":"JK Flip-Flop","paragraph":"JK flip-flop resolves the forbidden state of SR by making J=K=1 cause toggling of the output. J corresponds to Set and K to Reset."},{"type":"list","items":["J=0, K=0: Hold (Q unchanged)","J=1, K=0: Set (Q = 1)","J=0, K=1: Reset (Q = 0)","J=1, K=1: Toggle (Q = Q')"]},{"type":"math","math":"Q_{next} = J \\cdot Q' + K' \\cdot Q"},{"type":"paragraph","heading":"D Flip-Flop","paragraph":"The D (Data) flip-flop has a single input D. On the active clock edge, Q takes the value of D. It eliminates the forbidden state and simplifies sequential circuit design."},{"type":"list","items":["D=0, CLK rising edge: Q = 0","D=1, CLK rising edge: Q = 1","Q(next) = D at the clock edge"]},{"type":"math","math":"Q_{next} = D"},{"type":"paragraph","paragraph":"All three are edge-triggered in modern implementations to avoid race-around conditions. D flip-flops are most commonly used in registers; JK flip-flops in counters; SR in specialized sequential circuits."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partc-q4","number":4,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Explain Synchronous counters and sequence generator."}],"answer":{"summary":"Synchronous counters clock all flip-flops simultaneously; sequence generators are finite state machines designed to produce a specific bit pattern cyclically.","explanation":[{"type":"paragraph","heading":"Synchronous Counters","paragraph":"In a synchronous counter, all flip-flops receive the same clock signal simultaneously. The combinational logic determines which flip-flops toggle based on the current state. This eliminates the ripple delay of asynchronous counters."},{"type":"paragraph","heading":"4-bit Synchronous Up Counter (using T flip-flops)","paragraph":""},{"type":"list","items":["T0 = 1 (LSB always toggles)","T1 = Q0 (toggle when Q0=1)","T2 = Q0.Q1 (toggle when Q0=Q1=1)","T3 = Q0.Q1.Q2 (toggle when Q0=Q1=Q2=1)"]},{"type":"paragraph","paragraph":"Count sequence: 0000 -> 0001 -> 0010 -> 0011 -> ... -> 1111 -> 0000."},{"type":"paragraph","heading":"Advantages over Ripple Counter","paragraph":""},{"type":"list","items":["All flip-flops change state simultaneously -> no cumulative propagation delay","Faster maximum operating frequency","No glitches in decoded outputs"]},{"type":"paragraph","heading":"Sequence Generator","paragraph":"A sequence generator is a special counter whose output produces a specific non-binary sequence. It is designed as a finite state machine (FSM) by constructing a state transition table for the desired sequence and deriving the excitation equations."},{"type":"paragraph","heading":"Example: Generate sequence 001 -> 011 -> 111 -> 101 -> 001...","paragraph":"Design steps: (1) Write state table mapping current state to next state. (2) Derive JK (or D) flip-flop excitation equations using K-maps. (3) Implement with flip-flops and combinational logic."}]}},{"id":"rtu-ee-ec-eee-s4-digital-electronics-2024-partc-q5","number":5,"marks":10,"tags":["Part C"],"text":[{"type":"paragraph","content":"Describe A/D converter using voltage to frequency and voltage to time conversion."}],"answer":{"summary":"Voltage-to-frequency ADC converts analog voltage to a proportional frequency pulse train; voltage-to-time ADC measures the time for a ramp to cross the input voltage, then counts clock pulses in that time.","explanation":[{"type":"paragraph","heading":"Voltage-to-Frequency (V/F) A/D Converter","paragraph":"The V/F converter produces a pulse train whose frequency is proportional to the analog input voltage. A counter counts the pulses over a fixed gate time T, and the digital count represents the input voltage."},{"type":"svg","svg":""},{"type":"math","math":"f_{out} = K \\cdot V_{in}, \\quad \\text{Digital count} = f_{out} \\times T = K \\cdot V_{in} \\cdot T"},{"type":"list","items":["Advantages: high noise rejection (integrating behavior), simple, low cost","Disadvantage: slower conversion speed (limited by gate time T)"]},{"type":"paragraph","heading":"Voltage-to-Time (Dual-Slope / Ramp) A/D Converter","paragraph":"Also called the dual-slope integrating ADC. Phase 1: Integrate (charge up) the input Vin for a fixed time T1. Phase 2: Discharge (de-integrate) using a reference voltage Vref and count clock pulses until the integrator output crosses zero. The count N is proportional to Vin."},{"type":"math","math":"\\frac{V_{in}}{V_{ref}} = \\frac{N}{N_1}"},{"type":"paragraph","paragraph":"where N1 is the count during Phase 1 (fixed), and N is the count during Phase 2."},{"type":"list","items":["Excellent noise rejection due to integration over a full cycle","Clock frequency errors cancel (self-correcting)","Very accurate but slow (conversion time = T1 + T2)","Used in digital multimeters and high-accuracy instruments"]}]}}]}],"loading":false,"error":null}}}

Q2Digital Electronics

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Answer