RTUEE / EC / EEEYr 2023 · Sem 3

Digital System Design

2023

22 questions

Q12 marks

Determine the number of bits required to represent in floating point notation the exponent for decimal number in the range of .

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Q22 marks

How would an 8-bit microcomputer process this?

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Q32 marks

Implement using NAND gates only .

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Q42 marks

The input to a 2-input exclusive NOR gate are a variable and its inverse what is the output? Show truth table.

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Q52 marks

Convert into canonical form.

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Q62 marks

Show that a positive logic NAND gate is a negative logic NOR gate.

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Q72 marks

What is the difference between combinational and sequential circuits?

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Q82 marks

What is the difference between synchronous reset and asynchronous reset?

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Q92 marks

State the differences between Moore and Mealy State Machine.

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Q14 marks

Implement the following Boolean expression using multiplexer.

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Q34 marks

What are the advantages of tabulation method? A staircase light is controlled by two switches, one at top of the stair and another at the bottom of the staircase? (i) Make a truth table for this system (ii) Write logic equation (iii) Realize the circuit using AND-OR Gates

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Q54 marks

With respect to logic gate, explain the following terms: . Specify the value of these parameters for a standard TTL gate.

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Q64 marks

Many cars produced in Japan have an interlock system that allows the engine to start only if both the front seat occupant has their seats belt on. Construct a truth table to indicate whether the car may be started based upon whether a passenger is present and whether both passenger and the driver buckled their seat belt.

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Q110 marks

(a) A digital system has a 4-bit input from 0000 to 1111. Design a logic circuit that produces a high output whenever the equivalent decimal input is greater than 13. (b) Design the logic diagram of a circuit for addition/substraction. Use a control variable w and a circuit that functions as a full adder when w = 0, as a full substrator when w = 1.

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Q210 marks

Design the following - (a) 10 x 1K decoder using 8 x 256 decoder and additional logics (b) 32: 1 MUX using two 16:1 MUX's, one 2:1 MUX (c) Explain briefly the systematic procedure for using doesn't care condition. Define multilevel logic circuit with diagram.

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Q310 marks

(a) Toggle Flip-flop, popularly known as T flip-flop has following input- output relation. When input T = 0, the output does not change its state. For T = 1, the output toggles its value. Derive & implement the T flip-flop from JK flip-flop. (b) Design a sequence detector to detect a serial input sequence 1010. Draw its state diagram, state table, state assignment table and final implementation circuit.

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Q410 marks

(a) Which bipolar family is best suited for LSI? (i) Show the circuit of a 4-input NAND gate using CMOS transistor (ii) Repeat for a 4-input NOR gate (b) Compare the characteristics of different logic families.

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Q510 marks

(a) Explain and represent graphically the VLSI design flow using top down design. What is the role of simulation? (b) Discuss the requirement that led to the design of the VHDL language, which of these requirements where a software language would fall short in describing hardware.

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