Q5Operating Systems (Departmental Elective)
Question
Explain the concept of Demand Paging and Page Fault.
Answer
A deep dive into Demand Paging, explaining how the CPU's MMU mathematically triggers a hardware Page Fault to violently pause execution and load missing data from the Hard Drive.
Demand Paging is the absolute core architectural engine of modern Virtual Memory. Rather than aggressively loading an entire 5GB application into physical RAM simultaneously, the OS utilizes a "Lazy Swapper" (Pager). It mathematically slices the application into 4KB Pages, but initially loads ONLY the single specific page containing the startup code. The rest of the 5GB program physically remains on the slow Hard Disk Drive.
The Valid/Invalid Bit Architecture
To track this massive illusion, the OS maintains a Page Table. Every entry contains a strict hardware Valid/Invalid bit.
- Valid (v): Mathematically proves the Page is physically present in RAM.
- Invalid (i): Mathematically proves the Page is NOT in RAM (it is on the disk, or the address is illegal).
The Anatomy of a Page Fault
When the CPU executes a jump instruction to access code located on a page that is still on the disk, the following catastrophic hardware sequence occurs:
- 1. The Memory Management Unit (MMU) checks the Page Table and reads the "Invalid" bit.
- 2. The MMU instantly fires a massive hardware exception known as a Page Fault to the CPU.
- 3. The CPU violently halts the current process and traps into the OS Kernel.
- 4. The OS mathematically verifies the address is legal. It then commands the Hard Drive to physically spin up and fetch the missing 4KB page.
- 5. The OS aggressively hunts for a free 4KB Frame in physical RAM and slams the data into it.
- 6. The OS updates the Page Table, violently flipping the bit to "Valid".
- 7. The OS instantly rewinds the CPU's Program Counter and re-executes the exact instruction that crashed. This time, it succeeds flawlessly.