Q5Microprocessor and Interfaces

The 8086's Execution Unit contains only an integer ALU; it has no hardware support for floating-point arithmetic. Operations like floating-point multiplication, division, square roots, or trigonometric functions would have to be emulated entirely in software, which is extremely slow - often 100 times slower than dedicated hardware. The Intel 8087 Numeric Data Processor is a specialized coprocessor chip designed to plug this gap by executing such operations directly in hardware, conforming to the IEEE 754 floating-point standard and supporting extended data types (32-bit single precision, 64-bit double precision, 80-bit extended precision, and packed BCD).

How the 8087 Cooperates with the 8086

The 8087 is wired directly onto the 8086's local address/data bus and, critically, both chips fetch and monitor the exact same instruction stream in parallel. Ordinary instructions are decoded and executed by the 8086 as usual, while the 8087 ignores them. However, the 8086 instruction set reserves a special class of opcodes called ESC (Escape) instructions for numeric operations; when the 8086 encounters an ESC opcode, it treats it largely as a no-op for its own purposes (other than computing any memory operand address the 8087 will need) while the 8087, watching the same fetched byte stream, recognizes the ESC opcode as its own instruction and begins executing it internally.

Synchronization: TEST and WAIT

Because the 8087's numeric computations take multiple clock cycles to complete, the two processors must stay synchronized so the 8086 does not race ahead and use a result before the 8087 has finished computing it. The 8087 asserts its BUSY output while executing an instruction; this line is wired to the 8086's TEST' pin. Whenever the program needs to guarantee the numeric result is ready (typically the compiler inserts a WAIT instruction before any instruction that consumes the 8087's result), the 8086 executes WAIT, which repeatedly samples the TEST' pin and simply idles until BUSY goes low, confirming the 8087 has finished. This tight coupling lets the two chips behave, from the programmer's perspective, almost like a single processor with an extended, hardware-accelerated instruction set.

The 8086 can be configured in Maximum Mode (as opposed to Minimum Mode for simple single-processor systems), in which several of its status pins are reinterpreted to support external bus controller chips (like the 8288), enabling true multiprocessor system designs. Two broad architectures are used:

• Closely Coupled Configuration: Multiple processors (which may include coprocessors like the 8087, or additional 8086/8089 CPUs) share the same system bus, memory, and I/O space, communicating through shared memory locations and semaphores. This gives fast inter-processor communication but requires careful bus arbitration since only one device can drive the bus at a time.
• Loosely Coupled Configuration: Each processor has its own local bus, memory, and I/O, and processors communicate through a shared system bus or a dedicated communication channel/coprocessor (such as the 8089 I/O processor) only when necessary. This reduces bus contention at the cost of slower inter-processor communication.

Bus Arbitration Techniques

Whenever multiple bus masters (CPUs, DMA controllers, coprocessors) can request control of the shared system bus, a bus arbitration scheme is required to guarantee that only one master drives the bus at any instant, preventing electrical contention and data corruption.

• Daisy Chaining: All potential bus masters are connected in series to a single Bus Grant line that propagates from the bus controller through each device in turn. A device that does not need the bus passes the grant signal on to the next device in the chain; a device that does need it captures the signal and does not propagate it further. Priority is thus fixed by physical position in the chain (devices closer to the controller have higher priority), and the scheme is simple and requires very little extra hardware, but a device far down the chain can suffer significant delay waiting for the grant signal to propagate, and a single broken link disables arbitration for every device after it.
• Polling: A central bus controller sequentially polls each potential bus master (either by broadcasting an address on dedicated poll lines or cycling through device numbers) asking whether it needs the bus. Priority can be fixed (always poll in the same order) or rotating (each device gets a turn to be polled first, ensuring fairness). This avoids the chain-length delay problem of daisy chaining but consumes bus cycles for the polling process itself.
• Independent Requesting: Each potential bus master is given its own dedicated pair of Bus Request and Bus Grant lines directly to the bus controller, rather than sharing a common line. The controller can therefore see all pending requests simultaneously and grant the bus based on a fully software-programmable priority scheme (fixed, rotating, or based on real-time criteria). This is the fastest and most flexible technique, at the cost of requiring the most additional wiring and controller logic since the pin count grows linearly with the number of devices.