Q4Microprocessor and Interfaces

The 8255 Programmable Peripheral Interface is inherently an 8-bit device with an 8-bit data bus (D0-D7) and two internal address lines (A0, A1) used to select among Port A, Port B, Port C, and the Control Word Register. The 8086, however, has a 16-bit data bus physically split into an Even bank (D0-D7, enabled by address bit A0 = 0) and an Odd bank (D8-D15, enabled by the BHE' signal). Because the 8255 only understands an 8-bit bus, it must be wired entirely into one of these two banks, not straddled across both.

Even Address Interfacing

The 8255's D0-D7 pins connect directly to the 8086's D0-D7 lines. Because the 8086's A0 line is not physically available for connecting to the 8255's internal A0/A1 (it is consumed by the bank-select logic), the 8086's address lines A1 and A2 are instead wired to the 8255's internal A0 and A1 pins, effectively shifting the port-select addresses up by one bit position. The chip-select decoding logic uses the 8086's A0 = 0 condition (along with the higher-order address lines) to ensure the 8255 only responds to even physical addresses.

Odd Address Interfacing

Alternatively, the 8255's D0-D7 pins can be connected to the 8086's upper data lines D8-D15. In this configuration, the chip-select decoding logic uses the BHE' (Bus High Enable) signal, rather than A0, to enable the 8255 only when the CPU accesses an odd address. This scheme is necessary because the 8086 always transfers the high byte of a word over D8-D15, so any peripheral wired to the upper byte lane must be selected via BHE' instead of A0.

In both schemes, RD', WR', and RESET from the 8086 connect directly to the corresponding pins on the 8255, and the chip-select (CS') output from the address decoder (built from NAND gates or a 74LS138) is asserted only for the specific address range assigned to that 8255.

Keyboard Interfacing

Rather than dedicating one input line per key (which would be prohibitively expensive for a full keyboard), keys are arranged in a matrix of rows and columns, drastically reducing the number of I/O lines needed - an 8x8 matrix covers 64 keys using only 16 lines. An I/O device such as the 8255 (in software-scanned mode) or the dedicated 8279 Keyboard/Display controller drives the row lines one at a time (setting the active row low while others are high) and reads back the column lines to detect whether any key in that row is pressed. By cycling through all rows and recording which row/column intersection went active, the microprocessor identifies the specific key pressed and looks up its corresponding character code from a table. Because mechanical switches bounce (make and break contact several times within milliseconds of being pressed), the routine must apply either a software delay-and-recheck debounce loop or hardware debouncing (e.g., an RC filter or Schmitt trigger) before accepting the keypress as valid.

Display Interfacing

Seven-segment LED displays are commonly interfaced in multiplexed fashion to avoid dedicating a full port to every digit. All digits' corresponding segments (all the 'a' segments, all the 'b' segments, and so on) are wired in parallel to a single segment-data port, while each digit's common anode or cathode is individually controlled by a separate digit-select port. The microprocessor rapidly cycles through the digits: it outputs the segment pattern for digit 1 while enabling only digit 1's common line, then switches to digit 2's pattern and enables only digit 2, and so on, refreshing each digit for only a few milliseconds. Because this refresh happens fast enough (typically well above 50 Hz per digit), the human eye's persistence of vision perceives all digits as being lit continuously and simultaneously, even though only one digit is physically illuminated at any instant - this dramatically reduces the number of I/O lines and driving current compared to wiring every digit independently.