Q3Microprocessor and Interfaces

The 8086 supports 256 hardware and software interrupts. The lowest 1KB of memory (00000H to 003FFH) acts as the Interrupt Vector Table (IVT), holding 256 four-byte vectors (CS and IP addresses of ISRs).

• Hardware Interrupts: Initiated by external devices. It has NMI (Non-Maskable Interrupt, Type 2, cannot be ignored) and INTR (Maskable interrupt, controlled by IF flag).
• Software Interrupts: Initiated by INT n instructions in the program (e.g., INT 21H, INT 3).

The 8259 PIC handles multiple INTR requests. When an interrupt occurs:

• 1. Peripherals send interrupt requests to the 8259 (IR0-IR7).
• 2. The 8259 resolves priority and sends an INTR signal to the 8086.
• 3. If the 8086 IF flag is set, it acknowledges by sending two INTA (Interrupt Acknowledge) pulses.
• 4. First INTA: 8259 resolves priority internally.
• 5. Second INTA: 8259 places an 8-bit interrupt vector type number on the data bus.
• 6. The 8086 multiplies this type number by 4 to locate the vector in the IVT, pushes Flags, CS, and IP to the stack, disables interrupts (clears IF/TF), and jumps to the ISR address retrieved from the IVT.