Q3Microprocessor and Interfaces

The 8086 supports up to 256 distinct interrupt types, numbered 0 to 255. Each interrupt type is associated with a 4-byte vector - a 2-byte Instruction Pointer (IP) and a 2-byte Code Segment (CS) - stored in the Interrupt Vector Table (IVT), which occupies the lowest 1 KB of physical memory, addresses 00000H to 003FFH. The address of the vector for interrupt type N is computed simply as N x 4, and reading that 4-byte entry gives the CPU the CS:IP of the corresponding Interrupt Service Routine (ISR).

Categories of 8086 Interrupts

• Hardware Interrupts - NMI (Non-Maskable Interrupt): Connected to a dedicated pin, permanently assigned interrupt type 2, and cannot be disabled by software under any circumstances. It is reserved for catastrophic events such as an imminent power failure or a memory parity error.
• Hardware Interrupts - INTR (Maskable Interrupt): A general-purpose interrupt request line. The CPU only responds to it if the Interrupt Flag (IF) in the flag register is set (via STI); if IF is cleared (via CLI), INTR requests are ignored. Because INTR alone carries no type information, external hardware (typically a PIC) must supply the interrupt type number during the acknowledge cycle.
• Software Interrupts: Triggered explicitly by the INT n instruction embedded in a program, where n is any 8-bit type number from 0-255. These are commonly used to invoke operating system or BIOS services, for example INT 21H for DOS function calls. Additional special-case software interrupts include Type 0 (Divide Error, auto-triggered on division overflow), Type 1 (single-step, used by debuggers when the Trap Flag is set), and Type 3 (INT 3, the one-byte breakpoint instruction).

Common Interrupt Response Sequence

Regardless of source, once the CPU accepts an interrupt it performs the same sequence: it pushes the Flag register, then CS, then IP onto the stack (preserving the exact point of resumption and status flags); it clears the IF and TF flags to prevent nested maskable interrupts and single-stepping during the ISR; and it loads CS:IP from the corresponding IVT entry to begin executing the ISR. The ISR must end with IRET, which pops IP, CS, and Flags back off the stack to resume the interrupted program exactly where it left off.

Since the 8086 exposes only one maskable interrupt pin (INTR), the Intel 8259 Programmable Interrupt Controller is used to multiplex up to eight independent hardware interrupt request lines (IR0-IR7) from various peripherals onto that single line, while also supplying the interrupt type number the CPU needs to index into the IVT.

• 1. One or more peripherals assert their IR lines on the 8259, which latches these requests into its internal Interrupt Request Register (IRR).
• 2. The 8259's priority resolver picks the highest-priority pending, unmasked request and drives the INTR line to the CPU high.
• 3. If the CPU's IF flag is set, it completes its current instruction and responds with two INTA' (Interrupt Acknowledge) pulses on the bus.
• 4. During the first INTA' pulse, the 8259 freezes its priority decision and sets the corresponding bit in its In-Service Register (ISR), marking that interrupt as being serviced.
• 5. During the second INTA' pulse, the 8259 places an 8-bit interrupt type number (programmed during initialization) onto the data bus.
• 6. The CPU reads this type number, multiplies it by 4 to locate the correct 4-byte vector in the IVT, pushes Flags/CS/IP onto the stack, clears IF and TF, and jumps to the ISR address fetched from that vector.
• 7. At the end of the ISR, the software typically sends an End-Of-Interrupt (EOI) command back to the 8259 so it clears the corresponding ISR bit and becomes ready to service further requests on that or lower-priority lines.