Q7Microprocessor and Interfaces
Question
Explain the concept of memory interfacing techniques.
Answer
Memory interfacing techniques define how the microprocessor's address bus is decoded to select one specific memory chip out of many sharing the same bus, ranging from exhaustive absolute decoding to economical linear decoding, plus the 8086-specific even/odd bank scheme needed for its 16-bit data bus.
A microprocessor system is typically built from several smaller memory chips (ROM for the boot code, RAM for working data) that all share the same address, data, and control buses. Since only one chip may drive the data bus at a time, each chip has a Chip Select (CS') pin that must be driven low exactly when the CPU places an address within that chip's assigned range on the address bus. The circuitry that produces this signal is called address decoding, and there are two principal approaches.
Absolute (Full) Decoding
Every single address line, including the lines beyond what the chip itself needs, is fed into the decoding logic (typically NAND gates or a 3-to-8 decoder like the 74LS138). The chip's CS' is asserted for one, and only one, unique range of addresses with no overlap. This uses more decoding hardware but guarantees that each physical address maps to exactly one memory location - essential in systems that need the full available address space to be unambiguous, such as those running multiple memory-mapped peripherals.
Linear (Partial) Decoding
To save hardware cost, only a subset of the higher-order address lines is used to drive the CS' pin directly (or through a single gate), while the unused higher-order lines are left disconnected from the decode logic. This is simpler and cheaper but causes address foldback (or aliasing): because the unused lines can take either value without affecting chip selection, a single physical memory byte ends up accessible at multiple different addresses in the CPU's address space. This is acceptable in small, single-chip systems where the wasted address space is not needed for anything else.
Even and Odd Bank Interfacing (8086-specific)
The 8086 has a 16-bit data bus but many byte-wide memory chips only supply 8 bits at a time, so system memory is split into two banks: the Even bank, wired to data lines D0-D7 and selected when address line A0 = 0, and the Odd bank, wired to D8-D15 and selected using the BHE' (Bus High Enable) control signal. A word access spanning both banks lets the 8086 read or write 16 bits in a single bus cycle, while a byte access selects only the relevant bank, giving the processor flexibility to perform both 8-bit and 16-bit transfers over the same physical memory array.