RTUComputer ScienceYr 2024 · Sem 52024

Q5Microprocessor and Interfaces

Question

4 marks

Explain the concept of Serial Communication and UART.

Answer

Serial communication transmits data one bit at a time over a single wire pair, and the UART is the hardware that converts the microprocessor's parallel data into this serial stream (and back), framing each byte with start, stop, and optional parity bits for reliable asynchronous transfer.

Inside a microprocessor system, data moves in parallel - an entire byte travels simultaneously over 8 separate data-bus lines. Over long distances, however, running 8 or 16 parallel wires is expensive and susceptible to noise and skew between lines. Serial communication solves this by transmitting a single bit at a time over one signal line, trading raw speed for cost efficiency, simpler cabling, and robustness over long distances (e.g., RS-232, RS-485, or modern USB/UART links).

Synchronous vs Asynchronous Transfer

In synchronous serial communication, a separate clock line (or an embedded clock) keeps transmitter and receiver bit-for-bit synchronized. In asynchronous communication, no shared clock line exists; instead, each character is individually framed with timing markers so the receiver can resynchronize on every byte.

The UART and Its Framing

The Universal Asynchronous Receiver-Transmitter (UART) is the interface chip that performs this parallel-to-serial and serial-to-parallel conversion. On the transmit side, the CPU writes a parallel byte into the UART's transmit buffer; the UART then shifts it out bit by bit, wrapped in a defined frame:

  • Start Bit: A single low bit that signals the beginning of a new character, allowing the receiver's clock to synchronize.
  • Data Bits: Typically 5 to 8 bits carrying the actual character, sent least-significant-bit first.
  • Parity Bit (optional): A single bit set so the total number of 1-bits is even or odd, giving the receiver a basic single-bit error check.
  • Stop Bit(s): One or two high bits marking the end of the frame and providing a guaranteed idle interval before the next start bit.

On the receive side, the UART detects the falling edge of the start bit, samples the incoming line at the agreed baud rate to reconstruct each data bit, checks parity if enabled, verifies the stop bit, and finally presents the reassembled byte to the CPU as a parallel read, typically raising an interrupt or a status flag to signal that data is ready.

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