Q4Microprocessor and Interfaces

A microprocessor like the 8086 has only one general-purpose maskable interrupt input pin (INTR), but a real system needs to service many interrupt-driven peripherals - keyboard, timer, disk controller, and so on. The Intel 8259 PIC solves this by accepting up to eight individual interrupt request lines (IR0 through IR7) from peripherals, arbitrating between them, and presenting a single INTR signal to the CPU.

Internal Registers

• Interrupt Request Register (IRR): Latches all incoming interrupt requests that are currently pending.
• In-Service Register (ISR): Tracks which interrupt is currently being serviced by the CPU, preventing a lower priority interrupt from interrupting it.
• Interrupt Mask Register (IMR): Allows software to selectively disable (mask) individual IR lines.

Interrupt Handling Sequence

When one or more IR lines go active, the 8259's internal priority resolver picks the highest priority pending request (by default IR0 has the highest priority, IR7 the lowest, though the priority scheme is programmable) and drives the INTR line high. If the CPU's interrupt flag is enabled, it responds with two INTA (interrupt acknowledge) pulses. During the first pulse the 8259 freezes its priority decision; during the second pulse it places an 8-bit vector/type number, corresponding to the winning interrupt, onto the data bus. The CPU uses this number to index into the interrupt vector table and jump to the correct Interrupt Service Routine.

Cascading

A single 8259 handles only 8 lines. To support more devices, up to eight slave 8259s can be cascaded to one master 8259 through the CAS0-CAS2 lines, expanding the system to a maximum of 64 individually prioritized hardware interrupts - the scheme used in the original IBM PC/AT with two cascaded 8259s providing 15 usable interrupt lines.