Q4Microprocessor and Interfaces

The Intel 8255 Programmable Peripheral Interface is a massive 40-pin silicon IC strictly engineered to eradicate the I/O bottleneck of the 8085 microprocessor. It mathematically provides 24 completely programmable hardware I/O pins, structurally grouped into three 8-bit ports: Port A, Port B, and Port C. The absolute genius of the 8255 is that its mathematical behavior is entirely software-defined by writing an 8-bit binary string into its internal Control Word Register (CWR). When the CWR's Most Significant Bit ($D_7$) is set to 1, the chip activates its aggressive I/O modes.

Mode 0: Simple / Basic I/O

In Mode 0, the architecture is stripped down to its most primitive mathematical form. Ports A, B, and C function as simple, independent input or output ports. Data is violently pushed out to LEDs or pulled in from switches. There is absolutely no hardware handshaking or interrupt generation. The CPU simply executes OUT or IN instructions blindly.

Mode 1: Strobed I/O (Hardware Handshaking)

Mode 1 introduces highly complex, mathematically rigorous hardware handshaking to synchronize the blazing fast CPU with slow external peripherals (like an archaic printer). Port A and Port B act as the massive 8-bit data highways. However, Port C is completely cannibalized; its pins are violently repurposed to generate physical control signals.

• Input Handshaking: The peripheral sends 8 bits to Port A and violently pulses the STB' (Strobe) pin on Port C. The 8255 physically locks the data into a latch and instantly fires the IBF (Input Buffer Full) pin on Port C back to the peripheral, commanding it to halt data transmission. The 8255 then triggers a hardware interrupt to the CPU to fetch the data.
• Output Handshaking: The CPU blasts 8 bits into Port A. The 8255 violently pulses the OBF' (Output Buffer Full) pin to the printer. Once the printer physically prints the data, it fires an ACK' (Acknowledge) pulse back into Port C, mathematically informing the 8255 that it is ready for the next byte.

Mode 2: Bi-directional Strobed I/O

This is the most aggressive mode, strictly reserved for Port A. Port A mathematically becomes a massive two-way street, capable of both transmitting and receiving data on the exact same 8 pins. This requires extreme synchronization, utilizing a full 5 pins of Port C for complex bi-directional handshaking and bus arbitration, preventing fatal data collisions.

To physically connect the 8255 to the 8085 motherboard, the engineer must mathematically route the buses and construct a strict Address Decoding circuit using standard 74-series logic gates.

• Data Bus: The 8255's internal $D_0-D_7$ pins are wired directly to the 8085's demultiplexed Data Bus.
• Control Bus: The 8085's RD', WR', and RESET pins are physically wired straight into the identical pins on the 8255.
• Internal Port Selection ($A_0,A_1$): The 8255 possesses two internal address pins ($A_0$ and $A_1$). These are wired directly to the microprocessor's lowest address lines ($A_0,A_1$). They mathematically select the internal registers: - 00 = Port A - 01 = Port B - 10 = Port C - 11 = Control Word Register.
• Absolute Address Decoding (Chip Select): The 8255 remains completely mathematically dead until its CS' (Chip Select) pin receives a 0V signal. If we want the 8255 base address to be 80H (binary 1000 0000), we must wire the 8085's upper address lines ($A_2$ to $A_7$) through a massive NAND gate. Only when $A_7$ is 1, and $A_6$ through $A_2$ are all 0, will the NAND gate violently output a 0V pulse to the CS' pin, mathematically waking up the 8255 precisely at port addresses 80H, 81H, 82H, and 83H.