Q3Microprocessor and Interfaces
Question
Explain the concept of Interrupts in 8085 microprocessor.
Answer
A comprehensive technical breakdown of the 8085 Interrupt system, analyzing the strict hardware hierarchy of TRAP, RST 7.5, RST 6.5, RST 5.5, and INTR, and their vectored memory addresses.
In microprocessor engineering, an Interrupt is a catastrophic, high-priority electrical signal that violently forces the CPU to immediately suspend the execution of its current program. The CPU must mathematically save its current physical location (pushing the Program Counter onto the Stack) and aggressively jump to a specific physical memory address to execute an emergency sub-program known as the Interrupt Service Routine (ISR). The Intel 8085 possesses five strictly defined hardware interrupt pins, architected in a rigid mathematical priority hierarchy.
The Hardware Interrupt Hierarchy
When multiple hardware devices violently trigger interrupts simultaneously, the CPU relies on an absolute, unchangeable priority matrix to determine which signal to service first.
- 1. TRAP (Highest Priority): The absolute king of interrupts. TRAP is a Non-Maskable Interrupt (NMI). It absolutely cannot be disabled by software. It is strictly reserved for catastrophic system events like imminent power failures. It mathematically vectors the CPU to absolute address
0024H. - 2. RST 7.5: The second highest priority. It is uniquely edge-triggered (requires a physical transition from low to high voltage) and is heavily utilized for precise timing circuits. Vectors to address
003CH. - 3. RST 6.5: Third priority. Level-triggered. Vectors to address
0034H. - 4. RST 5.5: Fourth priority. Level-triggered. Vectors to address
002CH. - 5. INTR (Lowest Priority): The weakest interrupt. It is uniquely non-vectored. When INTR triggers, the CPU does not know where to jump. The external hardware must mathematically inject the specific
RSTinstruction opcode directly onto the Data Bus during the interrupt acknowledge cycle.
Masking and Execution Control
To prevent complete systemic chaos, engineers can aggressively control interrupts. The software instruction DI (Disable Interrupts) violently shuts down RST 7.5, 6.5, 5.5, and INTR. Only TRAP ignores DI. To reactivate the system, the engineer must execute EI (Enable Interrupts). Furthermore, the highly advanced SIM (Set Interrupt Mask) instruction allows engineers to mathematically disable or enable the RST interrupts individually at the bit level.