RTUComputer ScienceYr 2023 · Sem 52023

Q2Microprocessor and Interfaces

Question

4 marks

Describe the different addressing modes of 8085.

Answer

A detailed exploration of the five Addressing Modes of the 8085 microprocessor (Immediate, Register, Direct, Indirect, Implied), explaining exactly how the CPU mathematically locates operands in physical memory.

When a microprocessor executes a machine code instruction, it must mathematically locate the physical data (the operand) required to complete the operation. The specific architectural methodology the CPU utilizes to find this data is rigidly defined as the "Addressing Mode." The Intel 8085 is physically hardwired to support exactly five distinct addressing modes.

1. Immediate Addressing Mode

In this aggressively fast mode, the actual 8-bit or 16-bit mathematical data is physically hardcoded directly inside the instruction itself. The CPU does not need to search RAM for the data; it fetches it immediately after the opcode. - Example: MVI B, 45H (Violently moves the absolute hex value 45 directly into Register B). - Example: LXI H, 2050H (Loads the 16-bit value 2050H immediately into the HL register pair).

2. Register Addressing Mode

The fastest mode available. The mathematical operand is physically located entirely within one of the CPU's internal hardware registers (A, B, C, D, E, H, L). The CPU never touches the external memory buses, saving massive clock cycles. - Example: MOV A, B (Aggressively copies the 8-bit data from Register B into the Accumulator). - Example: ADD C (Mathematically adds the contents of C to the Accumulator).

3. Direct Addressing Mode

The instruction explicitly contains the absolute 16-bit physical memory address of the data. The CPU must halt, place the address on the Address Bus, and pull the data from RAM. - Example: LDA 2050H (Violently fetches the 8-bit data physically stored at RAM address 2050H and loads it into the Accumulator).

4. Register Indirect Addressing Mode

A highly advanced mode utilizing pointers. The instruction does NOT contain the data or the address. Instead, the instruction specifies a Register Pair (usually HL). The CPU reads the 16-bit value inside the HL pair, mathematically treats that value as a physical RAM address, and fetches the data from that external location. - Example: MOV A, M (The CPU looks at the HL pair, goes to that memory address, and copies the data to the Accumulator).

5. Implied / Implicit Addressing Mode

The absolute most compact mode. The instruction requires no operands because the physical target is mathematically implied by the opcode itself, almost always operating specifically on the Accumulator. - Example: CMA (Violently complements/inverts every single bit physically located in the Accumulator).

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