RTUComputer ScienceYr 2023 · Sem 52023

Q1Microprocessor and Interfaces

Question

4 marks

Explain the internal architecture of 8085 microprocessor.

Answer

A rigorous architectural breakdown of the Intel 8085 Microprocessor, detailing its 8-bit ALU, 16-bit address bus, and the specific functional roles of its internal hardware registers (Accumulator, B, C, D, E, H, L, PC, SP).

The Intel 8085 is an absolute legendary 8-bit microprocessor architected in 1976. It operates on a strict +5V physical power supply and utilizes an advanced 40-pin DIP (Dual In-line Package). Its internal silicon architecture is mathematically engineered to execute complex arithmetic and control operations through a heavily orchestrated system of buses, registers, and timing circuits.

1. The Arithmetic Logic Unit (ALU)

The ALU is the mathematical beating heart of the 8085. It is physically strictly limited to executing 8-bit binary operations, including Addition, Subtraction, logical AND, OR, EX-OR, and bit-shifting. It mathematically cannot multiply or divide; these must be simulated in software. The ALU aggressively relies on the Accumulator to hold one of the operands and violently stores the final calculated result back into the Accumulator.

2. The Register Array

To feed data into the ALU at blistering speeds, the 8085 possesses a highly optimized internal memory architecture known as the Register Array.

  • The Accumulator (Register A): The absolute most critical 8-bit register. It is inextricably linked to the ALU. Almost all mathematical operations require it.
  • General Purpose Registers: The CPU possesses six 8-bit auxiliary registers mathematically named B, C, D, E, H, and L. Engineers can aggressively combine them into 16-bit pairs (BC, DE, HL) to physically store 16-bit memory addresses. The HL pair specifically acts as the default Memory Pointer (M).
  • Program Counter (PC): A 16-bit hardware register that mathematically tracks the exact execution sequence. It always physically holds the absolute memory address of the next instruction the CPU must fetch.
  • Stack Pointer (SP): A 16-bit register dedicated to managing the LIFO Stack in RAM, violently crucial for executing CALL and RET subroutine instructions.

3. Timing and Control Unit

This physical circuit acts as the conductor. It receives the opcode, mathematically decodes it, and sends aggressive electrical control signals (RD, WR, ALE) across the motherboard to perfectly synchronize the RAM, the buses, and the peripherals with the CPU's internal clock frequency.

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