Q1Microprocessor and Interfaces

The 8086 architecture is divided into the Bus Interface Unit (BIU) and Execution Unit (EU). The BIU handles all data and addresses on the buses. The EU executes instructions. This split allows the two units to work concurrently, forming a simple two-stage pipeline that was a major performance innovation over the strictly sequential fetch-then-execute behavior of the 8085.

Bus Interface Unit (BIU)

• Instruction Queue: A 6-byte FIFO prefetch buffer. While the EU executes the current instruction, the BIU uses any free bus cycles to fetch subsequent opcode bytes into this queue, so the EU rarely has to wait for a fetch.
• Segment Registers: CS (Code), DS (Data), SS (Stack), ES (Extra) - four 16-bit registers that each hold the base of a 64KB memory segment.
• Address Generation Logic: Combines a segment register with a 16-bit offset to compute the 20-bit physical address placed on the address bus.
• Bus Control Logic: Generates and manages RD', WR', and other timing/control signals for all memory and I/O accesses.

Execution Unit (EU)

• 16-bit ALU: Performs arithmetic and logic operations, including native multiply and divide, which the 8085 lacked.
• General Registers: AX, BX, CX, DX, each splittable into 8-bit AH/AL style halves for byte-level compatibility.
• Pointer and Index Registers: SP, BP, SI, DI - used for stack addressing and efficient array/string operand addressing.
• Flag Register: A 16-bit register extending the 8085's flag set with additional flags such as Overflow, Direction, and Trap.
• Instruction Decoder and Control: Pulls opcodes from the BIU's instruction queue and generates the internal micro-operations to drive the ALU and registers.

Memory segmentation divides the 1MB physical memory into 64KB logical segments (Code, Data, Stack, Extra) addressed via segment registers and offsets. This scheme exists because the EU's registers are only 16 bits wide, which alone could only address 64 KB directly, yet the address bus is 20 bits wide, giving a full 1 MB range.

The segment register value is shifted left by 4 bits (equivalent to multiplying by 16, or 10H) and added to a 16-bit offset to produce the full 20-bit physical address. For example, if CS = 2000H and IP (the offset into the code segment) = 0300H, the physical address of the next instruction is (2000H x 10H) + 0300H = 20000H + 0300H = 20300H.

Because segments can overlap (any two segment bases within 64 KB of each other share addressable memory), the same physical byte can be reached by multiple different segment:offset pairs, which gives programmers flexibility in memory allocation and enables position-independent, relocatable code - a program can be loaded starting at any paragraph (16-byte) boundary simply by setting CS appropriately, without altering the instruction bytes themselves. This segmented model was also the direct precursor to memory protection and multitasking support introduced in later 80286/80386 protected-mode processors.

Each of the four segments has a specific role: the Code Segment (CS:IP) holds the instruction stream currently being fetched; the Data Segment (DS) holds the program's general variables, accessed by default with BX, SI and DI-based addressing modes; the Stack Segment (SS:SP or SS:BP) holds the runtime stack used for CALL/RET and PUSH/POP; and the Extra Segment (ES) provides an additional data area, used by default as the destination for string instructions like MOVS and STOS. A programmer can also explicitly override the default segment association of an addressing mode using a segment override prefix when an operand genuinely lives in a different segment than the default.