Q1Microprocessor and Interfaces
Question
Draw and explain the architecture of the 8085 microprocessor.
Answer
The 8085 architecture is built around an 8-bit ALU and accumulator, a flag register, six general-purpose registers usable as three 16-bit pairs, a program counter and stack pointer, and instruction decode/timing-control logic that together fetch, decode and execute instructions from memory.
The Intel 8085 is an 8-bit microprocessor fabricated as a single 40-pin IC, operating on a single +5V supply with a clock derived from an external crystal on the X1-X2 pins. Its internal architecture is organized into several cooperating functional blocks that together implement the fetch-decode-execute cycle for every instruction.
Arithmetic and Logic Unit (ALU)
The ALU is an 8-bit combinational circuit that performs addition, subtraction, increment, decrement, and logical operations (AND, OR, XOR, complement) as well as bit rotations. It always takes one operand from the Accumulator and, for two-operand instructions, the second from a register, memory, or an immediate byte, writing the result back into the Accumulator.
Accumulator and Flag Register
The Accumulator (Register A) is the primary 8-bit register through which almost all arithmetic and logic results flow. Adjacent to it is the 8-bit Flag register, which after every ALU operation updates five flip-flops: Sign (S), Zero (Z), Auxiliary Carry (AC), Parity (P), and Carry (CY). These flags drive conditional branch instructions such as JZ, JC and JNZ.
General-Purpose Registers
Six 8-bit registers - B, C, D, E, H, L - are available for temporary data storage. They can be used individually for 8-bit operations, or combined into three register pairs, B-C, D-E, and H-L, for instructions that need a 16-bit value. The H-L pair has a special role: it is frequently used as an indirect memory pointer (as in MOV A, M, which reads the byte at the address held in H-L).
Program Counter and Stack Pointer
The Program Counter (PC) is a 16-bit register holding the address of the next instruction byte to fetch; it increments automatically after each fetch and is overwritten directly by jump/call instructions. The Stack Pointer (SP) is a 16-bit register pointing to the top of a LIFO stack maintained in external RAM, used for PUSH/POP operations and automatically for return addresses during CALL/RET and interrupt servicing.
Instruction Register, Decoder, and Timing & Control Unit
Fetched opcodes are held in the Instruction Register and interpreted by the Instruction Decoder, which activates the specific internal control signals needed for that opcode. The Timing and Control Unit coordinates the whole chip, generating external bus control and status signals (RD', WR', ALE, IO/M', S0, S1) synchronized to the T-states of each machine cycle.
Interrupt Control and Serial I/O
Dedicated hardware manages the five interrupt inputs (TRAP, RST 7.5, RST 6.5, RST 5.5, INTR) including their individual masking via the SIM instruction. Two pins, SID and SOD, allow simple bit-serial data input and output directly through the accumulator without a separate UART chip.
Address/Data Buses
Internally, an 8-bit internal data bus links all these blocks. Externally, the lower 8 address lines are multiplexed with the data bus (AD0-AD7) to save pins, requiring an external latch driven by ALE to demultiplex them, while the upper 8 address lines (A8-A15) are dedicated output-only pins, giving a full 16-bit, 64 KB address range.