Q24Microprocessor and Microcontroller

The instruction MVI A, 32H mathematically commands the microprocessor to immediately load the hexadecimal value 32H directly into the Accumulator. This is a 2-byte instruction (Byte 1: Opcode 3EH, Byte 2: Data 32H). Its execution requires two distinct machine cycles: an Opcode Fetch cycle (4 T-states) followed by a Memory Read cycle (3 T-states), requiring a total of 7 T-states to fully execute.

Machine Cycle 1: Opcode Fetch (T1 - T4)

The microprocessor must fetch the opcode 3EH from memory.

• T1 State: The microprocessor forces the high-order address ($A_8-A_{15}$) onto the upper address bus. It forces the low-order address ($A_0-A_7$) onto the multiplexed $A{D}_0-A{D}_7$ bus. Crucially, it pulses the ALE (Address Latch Enable) signal HIGH, commanding the external latch to capture the lower address. Status signals are set: $IO/\bar{M}=0,S_1=1,S_0=1$.
• T2 State: ALE drops LOW. The $A{D}_0-A{D}_7$ bus completely floats, preparing to receive data. The microprocessor asserts the $\overline{RD}$ (Read) control signal LOW, commanding the memory chip to output its data.
• T3 State: The memory chip places the opcode (3EH) onto the $A{D}_0-A{D}_7$ bus. The microprocessor violently reads this data into its internal Instruction Register. The $\overline{RD}$ signal is pulled back HIGH.
• T4 State: Internal decoding. The buses are entirely ignored. The Instruction Decoder mathematically analyzes 3EH, recognizes it as MVI A, and realizes it must fetch one more byte of data from memory.

Machine Cycle 2: Memory Read (T1 - T3)

The microprocessor must fetch the immediate data 32H.

• T1 State: The Program Counter is incremented. The new address is forced onto the buses. ALE pulses HIGH to latch the new low-order address. Status signals change: $IO/\bar{M}=0,S_1=1,S_0=0$.
• T2 State: ALE drops LOW. The $A{D}_0-A{D}_7$ bus floats. The $\overline{RD}$ signal is asserted LOW.
• T3 State: The memory chip places the data byte (32H) onto the $A{D}_0-A{D}_7$ bus. The microprocessor reads this data and forcefully writes it directly into the Accumulator (Register A). The instruction is completely executed.