Q21Microprocessor and Microcontroller

An interrupt is a violent, external hardware signal that forces the microprocessor to instantaneously halt its current execution, preserve its current state, and completely redirect execution to a specialized subroutine called the Interrupt Service Routine (ISR). Once the ISR finishes, the CPU resumes its original task. The 8085 physically possesses five dedicated hardware interrupt pins.

Categorization of Interrupts

• Vectored vs. Non-Vectored: A vectored interrupt has a strictly hardcoded memory address (Vector Address) built into the microprocessor hardware. The CPU automatically jumps there. A non-vectored interrupt forces the external hardware device to supply the jump address over the data bus.
• Maskable vs. Non-Maskable: A maskable interrupt can be temporarily disabled (ignored) by the programmer utilizing the DI (Disable Interrupts) instruction. A non-maskable interrupt cannot be ignored; the CPU is mathematically forced to respond immediately.

The Five Hardware Interrupts (In Order of Priority)

• 1. TRAP (Highest Priority): - Properties: Non-maskable, Vectored. - Trigger: Both edge and level-triggered (to prevent false triggering from noise). - Vector Address: $0024H$. - Usage: Strictly reserved for catastrophic hardware emergencies, like imminent power failure or critical system faults.
• 2. RST 7.5 (Priority 2): - Properties: Maskable, Vectored. - Trigger: Positive Edge-triggered only. - Vector Address: $003CH$.
• 3. RST 6.5 (Priority 3): - Properties: Maskable, Vectored. - Trigger: Level-triggered. - Vector Address: $0034H$.
• 4. RST 5.5 (Priority 4): - Properties: Maskable, Vectored. - Trigger: Level-triggered. - Vector Address: $002CH$.
• 5. INTR (Lowest Priority): - Properties: Maskable, Non-Vectored. - Trigger: Level-triggered. - Execution: When INTR is triggered, the CPU sends an $\overline{INTA}$ (Interrupt Acknowledge) signal. The external hardware must then aggressively push an RST opcode onto the data bus, which provides the vector address.

Interrupt Masking Architecture

The maskable interrupts (RST 7.5, 6.5, 5.5) are governed by a complex internal Flip-Flop structure. They can be globally disabled via the DI instruction, and individually masked or unmasked by the programmer violently writing a specific 8-bit control word into the Accumulator and executing the SIM (Set Interrupt Mask) instruction.