Q18Microprocessor and Microcontroller

The 8085 microprocessor is engineered with a multiplexed Address/Data bus to save physical pins. Before any external memory can be successfully interfaced, this bus must be violently separated into two distinct, stable buses utilizing external hardware.

Part I: Demultiplexing the AD0-AD7 Bus

The lower 8 pins ($A{D}_0-A{D}_7$) carry the Low-Order Address ($A_0-A_7$) during the first clock cycle ($T_1$) and subsequently carry Data ($D_0-D_7$) during $T_2$ and $T_3$. To demultiplex this, we must physically insert an 8-bit D-Type Transparent Latch IC (universally the 74LS373 or 8212) onto the motherboard.

• Wiring: The 8 input pins of the 74LS373 latch are wired directly to the 8085's $A{D}_0-A{D}_7$ pins.
• Control: The 8085's ALE (Address Latch Enable) pin is wired directly to the Enable (G) pin of the 74LS373 latch.
• Execution: During $T_1$, the 8085 places the low-order address on the pins and pulses the ALE signal HIGH. The latch becomes transparent, allowing the address to flow through to its output pins. When ALE crashes LOW at the end of $T_1$, the latch rigidly locks that 8-bit address on its output pins (creating a permanent, stable $A_0-A_7$ bus). The 8085 can now freely use the $AD$ pins for data transfer, while the memory chip relies on the latched address.

Part II: Interfacing 1024 Bytes (1KB) of RAM

A 1024 Byte RAM chip requires exactly 10 address lines to uniquely select its internal memory cells, because $2^{10}=1024$. We will utilize address lines $A_0$ through $A_9$.

• Address Wiring: Connect the latched $A_0-A_7$ and the unlatched $A_8-A_9$ directly to the RAM chip's address pins.
• Data Wiring: Connect the 8085's multiplexed $A{D}_0-A{D}_7$ pins directly to the RAM chip's bidirectional $D_0-D_7$ pins.
• Address Decoding (Chip Select): The RAM chip possesses a Chip Select ($\overline{CS}$) pin that must be pulled LOW to activate it. We must ensure this RAM only turns on for a specific address range (e.g., $0000H$ to $03FFH$). We must utilize a decoder logic gate (like a NAND gate or a 74LS138 decoder). All remaining unused high-order address lines ($A_{10}$ through $A_{15}$) from the 8085 must be routed into this NAND gate. Only when $A_{10}-A_{15}$ are all exactly '0' will the NAND gate output a LOW signal to strictly enable the $\overline{CS}$ pin.
• Control Wiring: Combine the $IO/\bar{M}$ and $\overline{RD}$ signals from the 8085 through an OR gate to generate a strict $\overline{MEMR}$ (Memory Read) signal, wired to the RAM's Output Enable ($\overline{OE}$). Do the same for $\overline{WR}$ to generate $\overline{MEMW}$ for the RAM's Write Enable ($\overline{WE}$).