Q13Microprocessor and Microcontroller

A microprocessor is completely useless in isolation; it must communicate with external memory chips and I/O peripherals. This massive physical communication network is referred to as the System Bus. In the 8085 architecture, the System Bus is physically and logically partitioned into three highly distinct functional groups: the Address Bus, the Data Bus, and the Control Bus.

1. The Address Bus

The Address Bus is the targeting mechanism. It consists of exactly 16 parallel copper wires (labeled $A_0$ through $A_{15}$). - Directionality: It is strictly unidirectional. Electrical signals only flow OUT from the microprocessor toward the memory or peripherals. - Capacity: Because it possesses 16 bits, the microprocessor can mathematically generate $2^{16}=65,536$ unique binary addresses. This physically limits the 8085 to directly addressing a maximum of 64 Kilobytes (64KB) of memory. - Function: When the CPU needs to read or write, it asserts a specific 16-bit pattern on this bus to exclusively select one single memory location or one specific I/O port out of the thousands available on the motherboard.

2. The Data Bus

The Data Bus is the actual payload delivery system. It consists of exactly 8 parallel wires (labeled $D_0$ through $D_7$). - Directionality: It is strictly bidirectional. Data can flow INTO the microprocessor (during a Read operation) or OUT of the microprocessor (during a Write operation). - Capacity: Because it is exactly 8 bits wide, the 8085 is classified as an 8-bit microprocessor; it can only mathematically process or transfer 1 byte (8 bits) of information in a single machine cycle. - Multiplexing: To save physical pins on the IC, the lower 8 bits of the Address Bus ($A_0-A_7$) physically share the exact same wires as the Data Bus ($D_0-D_7$), utilizing time-division multiplexing controlled by the ALE signal.

3. The Control Bus

Unlike the Address and Data buses which are grouped related wires, the Control Bus is a loose collection of highly independent, specialized timing and status signals (like $\overline{RD}$, $\overline{WR}$, $IO/\bar{M}$, ALE). These signals act as the absolute traffic controllers, mathematically synchronizing the ultra-fast microprocessor with the significantly slower external memory chips, explicitly dictating when data should be placed on the bus and who is allowed to read it.