Q5Digital Electronics

The Set-Reset (SR) flip-flop obeys a strict logical protocol: Pulsing the Set input ($S=1,R=0$) physically forces the $Q$ output to a logic 1. Pulsing the Reset input ($S=0,R=1$) forces the $Q$ output to a logic 0. If both are deactivated ($0,0$), it infinitely holds its previous state. Activating both simultaneously ($1,1$) causes an unpredictable, fatal logic crash.