Q20Digital Electronics

The objective is to optimize the 4-variable Boolean function: $F(A,B,C,D)=\Sigma m(0,2,3,8,10,11,12,14)$ and physically implement the resulting logic utilizing absolutely nothing but universal NAND gates.

Step 1: Karnaugh Map Plotting

We construct a 16-cell K-map with axes $AB$ (vertical: 00, 01, 11, 10) and $CD$ (horizontal: 00, 01, 11, 10). We meticulously plot logic '1's in the cells corresponding to the provided decimal minterms: - Cell 0 (0000) - Cell 2 (0010) - Cell 3 (0011) - Cell 8 (1000) - Cell 10 (1010) - Cell 11 (1011) - Cell 12 (1100) - Cell 14 (1110)

Step 2: Strategic Grouping and Minimization

We seek the largest possible power-of-two groupings, aggressively wrapping around the map edges.

• Grouping 1 (The Four Corners): Cells 0, 2, 8, and 10 form a highly unique quad. The top row (0,2) and bottom row (8,10) wrap vertically. The left column (0,8) and right column (2,10) wrap horizontally. - Analyzing variables: $B$ remains constantly 0 ($B^{\prime }$). $D$ remains constantly 0 ($D^{\prime }$). - Extracted Term: $B^{\prime }{D}^{\prime }$
• Grouping 2 (Vertical Quad): Cells 2, 3, 10, and 11 form a contiguous quad spanning the top and bottom rows. - Analyzing variables: $B$ remains constantly 0 ($B^{\prime }$). $C$ remains constantly 1 ($C$). - Extracted Term: $B^{\prime }C$
• Grouping 3 (Horizontal Pair): Cells 12 and 14 form a pair on the $AB=11$ row. - Analyzing variables: $A$ is 1, $B$ is 1. $D$ remains constantly 0 ($D^{\prime }$). - Extracted Term: $AB{D}^{\prime }$

All 1s are successfully covered. The minimal Sum of Products (SOP) expression is: $F=B^{\prime }{D}^{\prime }+B^{\prime }C+AB{D}^{\prime }$

Step 3: Conversion to NAND-Only Logic

To physically construct this utilizing exclusively NAND gates, we must mathematically manipulate the SOP expression by applying a double-inversion (which changes nothing fundamentally) and systematically deploying De Morgan's Law to convert the central OR operations into NAND operations.

$F = ((B'D') + (B'C) + (ABD'))''

Applying De Morgan's Law to the inner inversion specifically breaks the massive sum into a multiplied product of individual complements: $F=[(B^{\prime }{D}^{\prime }{)}^{\prime }\cdot (B^{\prime }C{)}^{\prime }\cdot (AB{D}^{\prime }{)}^{\prime }{]}^{\prime }$

This final equation perfectly describes the hardware wiring: 1. Pass $B$ and $D$ through NAND inverters to generate $B^{\prime }$ and $D^{\prime }$. 2. Use a 2-input NAND gate to calculate $(B^{\prime }{D}^{\prime }{)}^{\prime }$. 3. Use a 2-input NAND gate to calculate $(B^{\prime }C{)}^{\prime }$. 4. Use a 3-input NAND gate to calculate $(AB{D}^{\prime }{)}^{\prime }$. 5. Route all three intermediate outputs into a final, massive 3-input NAND gate. The resulting output is $F$.