Q17Digital Electronics

An encoder is a fundamental combinational logic data compression circuit. It is explicitly engineered to mathematically translate data from a sprawling, unencoded format (where exactly one line out of many is active) into a highly compact, dense binary encoded format. An Octal-to-Binary encoder must accept 8 distinct input lines (representing the octal digits 0 through 7, labeled $D_0$ to $D_7$) and compress them down into a strict 3-bit binary output code ($Y_2,Y_1,Y_0$). The core operational assumption is that at any given nanosecond, exactly one input line will be active (HIGH).

Step 1: Truth Table Formulation

We construct a massive truth table mapping every possible valid input state to its corresponding binary output.

Inputs ($D_7\dots D_0$) $\to$ Outputs ($Y_2,Y_1,Y_0$) 00000001 ($D_0$ active) $\to$ 000 (Binary 0) 00000010 ($D_1$ active) $\to$ 001 (Binary 1) 00000100 ($D_2$ active) $\to$ 010 (Binary 2) 00001000 ($D_3$ active) $\to$ 011 (Binary 3) 00010000 ($D_4$ active) $\to$ 100 (Binary 4) 00100000 ($D_5$ active) $\to$ 101 (Binary 5) 01000000 ($D_6$ active) $\to$ 110 (Binary 6) 10000000 ($D_7$ active) $\to$ 111 (Binary 7)

Step 2: Boolean Logic Extraction

We systematically analyze the three output columns vertically to determine precisely which input lines force them to become logic HIGH (1).

Output $Y_0$ (The LSB): Analyzing the $Y_0$ column, it is strictly HIGH for decimal values 1, 3, 5, and 7. Therefore, the Boolean equation is simply the logical OR of these specific input lines. Equation: $Y_0=D_1+D_3+D_5+D_7$

Output $Y_1$ (The Middle Bit): Analyzing the $Y_1$ column, it is strictly HIGH for decimal values 2, 3, 6, and 7. Equation: $Y_1=D_2+D_3+D_6+D_7$

Output $Y_2$ (The MSB): Analyzing the $Y_2$ column, it is strictly HIGH for decimal values 4, 5, 6, and 7. Equation: $Y_2=D_4+D_5+D_6+D_7$

Step 3: Hardware Logic Gate Realization

The extracted Boolean equations are incredibly simple, containing absolutely no inverted inputs or complex AND logic. The entire Octal-to-Binary encoder architecture can be physically synthesized using strictly three massive 4-input OR gates.

1. Connect input lines $D_1,D_3,D_5,D_7$ into OR Gate 0. The output is $Y_0$. 2. Connect input lines $D_2,D_3,D_6,D_7$ into OR Gate 1. The output is $Y_1$. 3. Connect input lines $D_4,D_5,D_6,D_7$ into OR Gate 2. The output is $Y_2$. (Note: The $D_0$ input line is physically not connected to any gates. When $D_0$ is active, all other lines are 0, resulting in the correct output 000).