Q13Digital Electronics

The Half Adder is the absolute most fundamental combinational arithmetic circuit in digital electronics. It is explicitly engineered to mathematically add two single-bit binary inputs (A and B). Because $1+1$ equals binary $10$ (decimal 2), a single output bit is insufficient. Therefore, the Half Adder possesses exactly two outputs: a Sum bit (S) and a Carry bit (C). The rigorous Boolean logic for these outputs is: - Sum: $S=A\oplus B$ (Requires an Exclusive-OR gate) - Carry: $C=A\cdot B$ (Requires an AND gate)

While mathematically elegant, the Half Adder is fundamentally crippled in complex arithmetic because it physically lacks an input pin to accept a carry-over bit generated from a previous, lower-order addition stage. To cascade addition across multiple bits, a Full Adder is strictly required, which accepts three inputs: A, B, and a Carry-In ($C_{in}$).

Synthesizing a Full Adder using Half Adders

A complete Full Adder architecture can be brilliantly assembled by sequentially cascading exactly two Half Adders and adding a singular auxiliary OR gate.

Stage 1 (The First Half Adder): We route the two primary input bits, A and B, directly into the first Half Adder ($H{A}_1$). - $H{A}_1$ generates a partial intermediate sum: $S_{partial}=A\oplus B$. - $H{A}_1$ generates a potential first carry: $C_1=A\cdot B$.

Stage 2 (The Second Half Adder): We must now mathematically integrate the third input, the Carry-In ($C_{in}$). We route the $S_{partial}$ output from $H{A}_1$ into the first input of the second Half Adder ($H{A}_2$). We route the external $C_{in}$ signal directly into the second input of $H{A}_2$. - $H{A}_2$ calculates the final, absolute Sum for the entire circuit: $Su{m}_{Final}=S_{partial}\oplus C_{in}=(A\oplus B)\oplus C_{in}$. - $H{A}_2$ calculates a potential second carry: $C_2=S_{partial}\cdot C_{in}=(A\oplus B)\cdot C_{in}$.

Stage 3 (Carry Consolidation): The overall Full Adder circuit must generate a Carry-Out if either the first Half Adder generated a carry ($C_1$) OR the second Half Adder generated a carry ($C_2$). We physically route $C_1$ and $C_2$ into a standard 2-input OR gate. - $Carr{y}_{Final}=C_1+C_2=(A\cdot B)+((A\oplus B)\cdot C_{in})$. This flawlessly mathematically completes the Full Adder architecture using strictly minimal, modular components.