Q16Digital Electronics

In modern microprocessor arithmetic logic units (ALUs), hardware subtraction is rarely performed using direct borrow mechanics. Instead, the system aggressively utilizes 2's complement addition to effectively simulate subtraction ($A-B\to A+(-B)$). This brilliantly allows a single hardware adder circuit to execute both addition and subtraction. The process rigorously requires inverting the bits of the subtrahend and adding 1 to generate its 2's complement.

Given Binary Variables

$X=1010100$ (7 bits) $Y=1000011$ (7 bits)

Operation i) Execute X - Y

We must meticulously calculate the 2's complement of the subtrahend, $Y$. 1. 1's Complement of Y: Invert every bit of 1000011 $\to$ 0111100. 2. 2's Complement of Y: Add exactly 1 to the LSD $\to$ 0111100 + 1 = 0111101.

Now, perform standard binary addition: $X+(2^{\prime }scomplementofY)$. 1010100 (X) + 0111101 (2's Comp of Y) ------- 10010001 -------

Analysis of Result: The addition of two 7-bit numbers yielded an 8-bit result. The presence of this extra leftmost bit (the carry-out bit = 1) signifies two crucial facts: the final mathematical result is definitively positive, and the generated carry bit must be immediately discarded. Final True Result for X - Y = 0010001 (Decimal: $84-67=17$).

Operation ii) Execute Y - X

We must now meticulously calculate the 2's complement of the new subtrahend, $X$. 1. 1's Complement of X: Invert every bit of 1010100 $\to$ 0101011. 2. 2's Complement of X: Add exactly 1 to the LSD $\to$ 0101011 + 1 = 0101100.

Perform standard binary addition: $Y+(2^{\prime }scomplementofX)$. 1000011 (Y) + 0101100 (2's Comp of X) ------- 1101111 -------

Analysis of Result: The addition of the two 7-bit numbers yielded exactly a 7-bit result. The complete absence of a final carry-out bit (carry = 0) signifies a massive systemic alert: the final mathematical result is definitively negative, and the current binary sequence 1101111 is currently trapped in a 2's complement encoded state. It is not the true magnitude.

To extract the true magnitude, we must forcefully take the 2's complement of the result 1101111. 1. 1's Complement: Invert bits $\to$ 0010000. 2. 2's Complement: Add 1 $\to$ 0010001. We attach a negative sign to indicate the polarity. Final True Result for Y - X = -0010001 (Decimal: $67-84=-17$).